継続は力にゃりん。毎日続けることができるのか？

とばし
* verilog プリミティブゲート詳細
* verilog ユーザ定義プリミティブ詳細
* VHDL /, rem, mod, **
* VHDL コンフィギュレーション
* SystemC  wait_until
* SystemC  sc_module を直接継承
* SystemC  SC_HAS_PROCESS

不明
* VHDL  type したものを出力する方法？
* SystemC  sc_out_clk, sc_inout_clk
* SystemC  wait(n)
* SystemC  next_trigger()
* SystemC  sc_fixed, sc_ufixed

進捗

* 2007-04-18 (一時?)終了
* 2007-01-05 SystemC (って HDL?)
* 2006-08-20 VHDL
* 2006-07-15 Verilog 2001
* 2006-04-01 Verilog-HDL

!2007-04-18 Wed

sc_inout

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in    <bool> in;
    sc_inout <bool> io;
  
    bool data;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in << io;
    }
  };
  
  void buffer::buf(void)
  {
    if (in.read()) {
      data = io.read();
    } else {
      io.write(data);
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> io;
  
    buffer b1("buffer");
    b1(in, io);
  
    sc_initialize();
  
    in = true; io = true; sc_start(1, SC_NS);
    cout << in << " " << io << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << io << endl;
  
    in = true; io = false; sc_start(1, SC_NS);
    cout << in << " " << io << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << io << endl;
  
    return 0;
  }
で、
  1 1
  0 1
  1 0
  0 0

* 推測で使ってみたが OK?
* data を関数のローカル変数にすると「0 1」の部分が「0 64」と変に

!2007-04-17 Tue

階層化チャネル

基本的に『SystemCプログラミング基礎講座』(塚田 雄一 著、翔泳社)のまま

  #include <iostream>
  #include "systemc.h"
  
  class sc_fifo_interface : virtual public sc_interface
  {
  public:
    virtual void write(sc_uint<8> data) = 0;
    virtual sc_uint<8> read() = 0;
  };
  
  struct fifo_channel : public sc_module, public sc_fifo_interface
  {
  public:
    sc_uint<8> fifo_data[16];
    int write_cnt;
    int read_cnt;
  
    virtual void write(sc_uint<8> data);
    virtual sc_uint<8> read();
  
    SC_CTOR(fifo_channel)
    {
      write_cnt = 0;
      read_cnt  = 0;
    }
  };
  
  void fifo_channel::write(sc_uint<8> data)
  {
    fifo_data[write_cnt] = data;
    write_cnt++;
    if (write_cnt >= 16) {
      write_cnt = 0;
    }
  }
  
  sc_uint<8> fifo_channel::read()
  {
    sc_uint<8> data;
  
    if (write_cnt != read_cnt) {
      data = fifo_data[read_cnt];
      read_cnt++;
      if (read_cnt >= 16)
        read_cnt = 0;
    } else {
      data = -1;
    }
  
    return data;
  }
  
  SC_MODULE(FIFOs)
  {
    sc_port<sc_fifo_interface> out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    for (int i = 0; i < 10; i++) {
      out->write(i);
      cout << "i : " << i << "  out : " << i << endl;
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_port<sc_fifo_interface> in;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOr)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    while (1) {
      cout << "in : " << in->read() << endl;
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    fifo_channel fifo("channel");
  
    FIFOs fs("FIFOs");
    FIFOr fr("FIFOr");
    fs.out(fifo);
    fr.in(fifo);
  
    sc_initialize();
  
    return 0;
  }
で、
  i : 0  out : 0
  i : 1  out : 1
  i : 2  out : 2
  i : 3  out : 3
  i : 4  out : 4
  i : 5  out : 5
  i : 6  out : 6
  i : 7  out : 7
  i : 8  out : 8
  i : 9  out : 9
  in : 0
  in : 1
  in : 2
  in : 3
  in : 4
  in : 5
  in : 6
  in : 7
  in : 8
  in : 9
  in : 255
  in : 255
     ...

止らないぞ〜

!2007-04-16 Mon

2007-04-15 Sun で、SC_THREAD, SC_CTHREAD 混在

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FIFOs)
  {
    sc_fifo_out<sc_uint<8> > out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    for (int i = 0; i < 10; i++) {
      out->write(i);
      cout << "i : " << i << "  out : " << i << endl;
    }
  }
  
  SC_MODULE(FIFOt)
  {
    sc_fifo_in <sc_uint<8> > in;
    sc_in<bool> clk;
    sc_out<sc_uint<8> > out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOt)
    {
      SC_CTHREAD(FIFO_proc, clk);
    }
  };
  
  void FIFOt::FIFO_proc(void)
  {
    while (1) {
      sc_uint<8> x = in->read();
      out->write(x);
      cout << "io : " << x << endl;
      wait();
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_in<bool> clk;
    sc_in<sc_uint<8> > in;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOr)
    {
      SC_CTHREAD(FIFO_proc, clk);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    while (1) {
      cout << "in : " << in->read() << endl;
      wait();
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock CLK("CLK", 10);
    sc_fifo<sc_uint<8> > fifo;
    sc_signal<sc_uint<8> > s;
  
    FIFOs fs("FIFOs");
    FIFOt ft("FIFOt");
    FIFOr fr("FIFOr");
  
    fs.out(fifo);
    ft.in (fifo);
  
    ft.clk(CLK);
    ft.out(s);
    fr.clk(CLK);
    fr.in (s);
  
    //sc_initialize();
    sc_start(200, SC_NS);
  
    return 0;
  }
で、
  i : 0  out : 0
  i : 1  out : 1
  i : 2  out : 2
  i : 3  out : 3
  i : 4  out : 4
  i : 5  out : 5
  i : 6  out : 6
  i : 7  out : 7
  i : 8  out : 8
  i : 9  out : 9
  io : 0
  in : 0
  io : 1
  in : 0
  io : 2
  in : 1
  io : 3
  in : 2
  io : 4
  in : 3
  io : 5
  in : 4
  io : 6
  in : 5
  io : 7
  in : 6
  io : 8
  in : 7
  io : 9
  in : 8
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9

    sc_fifo<sc_uint<8> > fifo;
を
    sc_fifo<sc_uint<8> > fifo(3);
にすると、
  i : 0  out : 0
  i : 1  out : 1
  i : 2  out : 2
  io : 0
  in : 0
  i : 3  out : 3
  io : 1
  in : 0
  i : 4  out : 4
  io : 2
  in : 1
  i : 5  out : 5
  io : 3
  in : 2
  i : 6  out : 6
  io : 4
  in : 3
  i : 7  out : 7
  io : 5
  in : 4
  i : 8  out : 8
  io : 6
  in : 5
  i : 9  out : 9
  io : 7
  in : 6
  io : 8
  in : 7
  io : 9
  in : 8
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9
  in : 9

!2007-04-15 Sun

三つをつなげて

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FIFOs)
  {
    sc_fifo_out<sc_uint<8> > out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    for (int i = 0; i < 10; i++) {
      out->write(i);
      cout << "i : " << i << "  out : " << i << endl;
    }
  }
  
  SC_MODULE(FIFOt)
  {
    sc_fifo_in <sc_uint<8> > in;
    sc_fifo_out<sc_uint<8> > out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOt)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOt::FIFO_proc(void)
  {
    while (1) {
      sc_uint<8> x = in->read();
      out->write(x);
      cout << "io : " << x << endl;
      //wait();
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_fifo_in<sc_uint<8> > in;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOr)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    while (1) {
      cout << "in : " << in->read() << endl;
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_fifo<sc_uint<8> > fifo1, fifo2;
  
    FIFOs fs("FIFOs");
    FIFOt ft("FIFOt");
    FIFOr fr("FIFOr");
  
    fs.out(fifo1);
    ft.in (fifo1);
  
    ft.out(fifo2);
    fr.in (fifo2);
  
    sc_initialize();
  
    return 0;
  }
で、
  i : 0  out : 0
  i : 1  out : 1
  i : 2  out : 2
  i : 3  out : 3
  i : 4  out : 4
  i : 5  out : 5
  i : 6  out : 6
  i : 7  out : 7
  i : 8  out : 8
  i : 9  out : 9
  in : io : 0
  io : 1
  io : 2
  io : 3
  io : 4
  io : 5
  io : 6
  io : 7
  io : 8
  io : 9
  0
  in : 1
  in : 2
  in : 3
  in : 4
  in : 5
  in : 6
  in : 7
  in : 8
  in : 9
  in : 

!2007-04-14 Sat

デストラクタ

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  
    ~buffer() {
      cout << "destructor" << endl;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1
  0 0
  destructor

!2007-04-13 Fri

sc_lv

2007-04-12 Thu で sc_bv -> sc_lv

で、
  00000000 00000000
  01010101 01010101

!2007-04-12 Thu

sc_bv

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <sc_bv<8> >  in;
    sc_out<sc_bv<8> > out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_bv<8> > in;
    sc_signal<sc_bv<8> > out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = "00000000";  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = "01010101"; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  00000000 00000000
  01010101 01010101

!2007-04-11 Wed

sc_fifo data_read_event(), data_written_event()

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FIFOs)
  {
    sc_fifo_out<bool> out;
  
    void FIFO_proc(void);
    void FIFO_proc2(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
      SC_THREAD(FIFO_proc2);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    bool x = true;
  
    for (int i = 0; i < 10; i++) {
      out->write(x);
      cout << "i : " << i << "  out : " << x << endl;
      x = !x;
    }
  }
  
  void FIFOs::FIFO_proc2(void)
  {
    while (1) {
      wait(out->data_read_event());
      cout << "out->data_read_event()" << endl;
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_fifo_in<bool> in;
  
    void FIFO_proc(void);
    void FIFO_proc2(void);
  
    SC_CTOR(FIFOr)
    {
      SC_THREAD(FIFO_proc);
      SC_THREAD(FIFO_proc2);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    while (1) {
      cout << "in : " << in->read() << endl;
    }
  }
  
  void FIFOr::FIFO_proc2(void)
  {
    while (1) {
      wait(in->data_written_event());
      cout << "in->data_written_event()" << endl;
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_fifo<bool> fifo;
  
    FIFOs fs("FIFOs");
    FIFOr fr("FIFOr");
    fs.out(fifo);
    fr.in(fifo);
  
    sc_initialize();
  
    return 0;
  }
で、
  i : 0  out : 1
  i : 1  out : 0
  i : 2  out : 1
  i : 3  out : 0
  i : 4  out : 1
  i : 5  out : 0
  i : 6  out : 1
  i : 7  out : 0
  i : 8  out : 1
  i : 9  out : 0
  in : in->data_written_event()
  1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : out->data_read_event()

動作検証できているか怪しい…

以下のように変えてみる
  ***************
  *** 68,74 ****
    
    int sc_main(int argc, char *argv[])
    {
  !   sc_fifo<bool> fifo;
    
      FIFOs fs("FIFOs");
      FIFOr fr("FIFOr");
  --- 68,74 ----
    
    int sc_main(int argc, char *argv[])
    {
  !   sc_fifo<bool> fifo(3);
    
      FIFOs fs("FIFOs");
      FIFOr fr("FIFOr");
と、
  i : 0  out : 1
  i : 1  out : 0
  i : 2  out : 1
  in : in->data_written_event()
  1
  in : 0
  in : 1
  in : out->data_read_event()
  i : 3  out : 0
  i : 4  out : 1
  i : 5  out : 0
  0
  in : 1
  in : 0
  in : in->data_written_event()
  i : 6  out : 1
  i : 7  out : 0
  i : 8  out : 1
  out->data_read_event()
  in->data_written_event()
  1
  in : 0
  in : 1
  in : out->data_read_event()
  i : 9  out : 0
  0
  in : in->data_written_event()
  out->data_read_event()

!2007-04-10 Tue

ポート配列(2007-01-12 Fri 改)

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(AND)
  {
    sc_in <bool> in[2];
    sc_out<bool> out;
  
    void and(void);
  
    SC_CTOR(AND)
    {
      SC_METHOD(and);
      sensitive << in[0] << in[1];
    }
  };
  
  void AND::and(void)
  {
    out.write(in[0].read() & in[1].read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in[2];
    sc_signal<bool> out;
  
    AND x("and");
    x(in[0], in[1], out);
  
    sc_initialize();
  
    in[0] = false; in[1] = false; sc_start(1, SC_NS);
    cout << in[0] << " " << in[1] << " " << out << endl;
  
    in[0] = false; in[1] = true;  sc_start(1, SC_NS);
    cout << in[0] << " " << in[1] << " " << out << endl;
  
    in[0] = true;  in[1] = true;  sc_start(1, SC_NS);
    cout << in[0] << " " << in[1] << " " << out << endl;
  
    return 0;
  }
で、
  0 0 0
  0 1 0
  1 1 1

試しに、
    AND x("and");
    x.in[0](in[0]);
    x.in[1](in[1]);
    x.out(out);
としてみたが、コンパイル & 実行できてしまった〜

!2007-04-09 Mon

systemc 2.2.0 で、SC_CTHREAD、reset_signal_is (watching の代り？)

2007-04-05 Thu との差
  ***************
  *** 15,21 ****
      SC_CTOR(COUNTER)
      {
        SC_CTHREAD(proc, CLK.pos());
  !     watching(RST.delayed() == true);
      }
    };
    
  --- 15,21 ----
      SC_CTOR(COUNTER)
      {
        SC_CTHREAD(proc, CLK.pos());
  !     reset_signal_is(RST, true);
      }
    };
    
で、
  Info: (I804) /IEEE_Std_1666/deprecated: sc_initialize() is deprecated: use sc_start(SC_ZERO_TIME)
  COUNTER::proc() cnt: 0
  0 s: 1 0
  2 ns:  1 0
  10 ns:: 0 0
  COUNTER::proc() cnt: 1
  12 ns:  1 1
  20 ns:: 0 1
  COUNTER::proc() cnt: 2
  22 ns:  1 2
  30 ns:: 0 2
  COUNTER::proc() cnt: 3
  32 ns:  1 3
  40 ns:: 0 3
  COUNTER::proc() cnt: 4
  42 ns:  1 4
  50 ns:: 0 4
  COUNTER::proc() cnt: 5
  52 ns:  1 5
  60 ns:: 0 5
  60 ns: 0 5
  COUNTER::proc() cnt: 0
  62 ns: 1 0
  
  Info: (I804) /IEEE_Std_1666/deprecated: You can turn off warnings about
               IEEE 1666 deprecated features by placing this method call as the
               first statement in your sc_main() function:
  
    sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
  
  

!2007-04-08 Sun

vcd 出力、内部信号を出力

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  SC_MODULE(buffer2)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    sc_signal<bool> tmp;
    void buf(void);
  
    buffer *b1;
    buffer *b2;
  
    SC_CTOR(buffer2)
    {
      b1 = new buffer("b1");
      (*b1)(in, tmp);
      b2 = new buffer("b2");
      b2->in(tmp);
      b2->out(out);
  
      SC_METHOD(buf);
      sensitive << tmp;
    }
  };
  
  void buffer2::buf(void)
  {
    out.write(tmp.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
    buffer2 *b;
  
    b = new buffer2("buffer");
    (*b)(in, out);
  
    sc_trace_file *trace_f;
    trace_f = sc_create_vcd_trace_file("2007040800");
    ((vcd_trace_file *)trace_f) -> sc_set_vcd_time_unit(-9);
  
    sc_trace(trace_f, in, "In");
    sc_trace(trace_f, out, "Out");
    sc_trace(trace_f, b->tmp, "b.tmp");
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << b->tmp << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << b->tmp << " " << out << endl;
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << b->tmp << " " << out << endl;
  
    return 0;
  }
で、
  1 1 1
  0 0 0
  1 1 1

!2007-04-07 Sat

vcd 出力、内部信号を出力

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  SC_MODULE(buffer2)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    sc_signal<bool> tmp;
    void buf(void);
  
    buffer *b1;
    buffer *b2;
  
    SC_CTOR(buffer2)
    {
      b1 = new buffer("b1");
      (*b1)(in, tmp);
      b2 = new buffer("b2");
      b2->in(tmp);
      b2->out(out);
  
      SC_METHOD(buf);
      sensitive << tmp;
    }
  };
  
  void buffer2::buf(void)
  {
    out.write(tmp.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer2 b("buffer");
    b(in, out);
  
    sc_trace_file *trace_f;
    trace_f = sc_create_vcd_trace_file("2007040700");
    ((vcd_trace_file *)trace_f) -> sc_set_vcd_time_unit(-9);
  
    sc_trace(trace_f, in, "In");
    sc_trace(trace_f, out, "Out");
    sc_trace(trace_f, b.tmp, "b.tmp");
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << b.tmp << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << b.tmp << " " << out << endl;
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << b.tmp << " " << out << endl;
  
    return 0;
  }
で、
  1 1 1
  0 0 0
  1 1 1

!2007-04-06 Fri

SC_CTHREAD、while の中に wait 複数

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(COUNTER)
  {
    sc_in_clk   CLK;
    sc_out<sc_uint<2> > out;
  
    void proc(void);
  
    SC_CTOR(COUNTER)
    {
      SC_CTHREAD(proc, CLK.pos());
    }
  };
  
  void COUNTER::proc(void)
  {
    sc_uint<2> cnt = 0;
  
    while (1) {
      cout << "COUNTER::proc() 1 cnt: " << cnt << endl;
      out.write(cnt); cnt++;
      wait();
  
      cout << "COUNTER::proc() 2 cnt: " << cnt << endl;
      out.write(cnt); cnt++;
      wait();
  
      cout << "COUNTER::proc() 3 cnt: " << cnt << endl;
      out.write(cnt); cnt++;
      wait();
  
      cout << "COUNTER::proc() 4 cnt: " << cnt << endl;
      out.write(cnt); cnt++;
      wait();
  
      cout << "COUNTER::proc() 5 cnt: " << cnt << endl;
      out.write(cnt); cnt++;
      wait();
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS);
    sc_signal<sc_uint<2> > out;
  
    COUNTER cnt("COUNTER");
    cnt(Clk, out);
  
    sc_initialize();
  
    cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
  
    for (int i = 0; i < 10; i++) {
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ":  " << Clk << " " << out << endl;
  
      sc_start(8, SC_NS);
      cout << sc_time_stamp() << ":: " << Clk << " " << out << endl;
    }
  
    return 0;
  }
で、
  COUNTER::proc() 1 cnt: 0
  0 s: 1 0
  2 ns:  1 0
  10 ns:: 0 0
  COUNTER::proc() 2 cnt: 1
  12 ns:  1 1
  20 ns:: 0 1
  COUNTER::proc() 3 cnt: 2
  22 ns:  1 2
  30 ns:: 0 2
  COUNTER::proc() 4 cnt: 3
  32 ns:  1 3
  40 ns:: 0 3
  COUNTER::proc() 5 cnt: 0
  42 ns:  1 0
  50 ns:: 0 0
  COUNTER::proc() 1 cnt: 1
  52 ns:  1 1
  60 ns:: 0 1
  COUNTER::proc() 2 cnt: 2
  62 ns:  1 2
  70 ns:: 0 2
  COUNTER::proc() 3 cnt: 3
  72 ns:  1 3
  80 ns:: 0 3
  COUNTER::proc() 4 cnt: 0
  82 ns:  1 0
  90 ns:: 0 0
  COUNTER::proc() 5 cnt: 1
  92 ns:  1 1
  100 ns:: 0 1

!2007-04-05 Thu

SC_CTHREAD、watching

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(COUNTER)
  {
    sc_in<bool> RST;
    sc_in_clk   CLK;
    sc_out<int> out;
  
    void proc(void);
  
    SC_CTOR(COUNTER)
    {
      SC_CTHREAD(proc, CLK.pos());
      watching(RST.delayed() == true);
    }
  };
  
  void COUNTER::proc(void)
  {
    int cnt = 0;
  
    while (1) {
      cout << "COUNTER::proc() cnt: " << cnt << endl;
      out.write(cnt);
      cnt++;
      if (cnt >= 10) {
        cnt = 0;
      }
      wait();
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS);
    sc_signal<bool> reset;
    sc_signal<int>  out;
  
    COUNTER cnt("COUNTER");
    cnt(reset, Clk, out);
  
    sc_initialize();
  
    cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
  
    for (int i = 0; i < 6; i++) {
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ":  " << Clk << " " << out << endl;
  
      sc_start(8, SC_NS);
      cout << sc_time_stamp() << ":: " << Clk << " " << out << endl;
    }
  
    reset = true;
    cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
    sc_start(2, SC_NS);
    cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
  
    return 0;
  }
で、
  COUNTER::proc() cnt: 0
  0 s: 1 0
  2 ns:  1 0
  10 ns:: 0 0
  COUNTER::proc() cnt: 1
  12 ns:  1 1
  20 ns:: 0 1
  COUNTER::proc() cnt: 2
  22 ns:  1 2
  30 ns:: 0 2
  COUNTER::proc() cnt: 3
  32 ns:  1 3
  40 ns:: 0 3
  COUNTER::proc() cnt: 4
  42 ns:  1 4
  50 ns:: 0 4
  COUNTER::proc() cnt: 5
  52 ns:  1 5
  60 ns:: 0 5
  60 ns: 0 5
  COUNTER::proc() cnt: 0
  62 ns: 1 0

!2007-04-04 Wed

SC_CTHREAD、カウンタ記述

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(COUNTER)
  {
    sc_in_clk   CLK;
    sc_out<int> out;
  
    void proc(void);
  
    SC_CTOR(COUNTER)
    {
      SC_CTHREAD(proc, CLK.pos());
    }
  };
  
  void COUNTER::proc(void)
  {
    int cnt = 0;
  
    while (1) {
      cout << "COUNTER::proc() cnt: " << cnt << endl;
      out.write(cnt);
      cnt++;
      if (cnt >= 10) {
        cnt = 0;
      }
      wait();
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS);
    sc_signal<int> out;
  
    COUNTER cnt("COUNTER");
    cnt(Clk, out);
  
    sc_initialize();
  
    cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
  
    for (int i = 0; i < 12; i++) {
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ":  " << Clk << " " << out << endl;
  
      sc_start(8, SC_NS);
      cout << sc_time_stamp() << ":: " << Clk << " " << out << endl;
    }
  
    return 0;
  }
で、
  COUNTER::proc() cnt: 0
  0 s: 1 0
  2 ns:  1 0
  10 ns:: 0 0
  COUNTER::proc() cnt: 1
  12 ns:  1 1
  20 ns:: 0 1
  COUNTER::proc() cnt: 2
  22 ns:  1 2
  30 ns:: 0 2
  COUNTER::proc() cnt: 3
  32 ns:  1 3
  40 ns:: 0 3
  COUNTER::proc() cnt: 4
  42 ns:  1 4
  50 ns:: 0 4
  COUNTER::proc() cnt: 5
  52 ns:  1 5
  60 ns:: 0 5
  COUNTER::proc() cnt: 6
  62 ns:  1 6
  70 ns:: 0 6
  COUNTER::proc() cnt: 7
  72 ns:  1 7
  80 ns:: 0 7
  COUNTER::proc() cnt: 8
  82 ns:  1 8
  90 ns:: 0 8
  COUNTER::proc() cnt: 9
  92 ns:  1 9
  100 ns:: 0 9
  COUNTER::proc() cnt: 0
  102 ns:  1 0
  110 ns:: 0 0
  COUNTER::proc() cnt: 1
  112 ns:  1 1
  120 ns:: 0 1

* int でなくて char だと出力値がおかしなものに。どうすれば？
* sc_uint<8> だと大丈夫だった

!2007-04-03 Tue

2007-04-02 Mon はこれで良かったか？
相違

  ***************
  *** 8,14 ****
    {
      sc_in_clk    CLK;
      sc_out<bool> out;
  -   bool val;
    
      void proc(void);
    
  --- 8,13 ----
  ***************
  *** 20,26 ****
    
    void FF::proc(void)
    {
  !   val = true;
    
      while (1) {
        cout << "FF::proc() in   val: " << val << endl;
  --- 19,25 ----
    
    void FF::proc(void)
    {
  !   bool val = true;
    
      while (1) {
        cout << "FF::proc() in   val: " << val << endl;
で、
  FF::proc() in   val: 1
  FF::proc() out  val: 0
  0 s: 1 1
  2 ns: 1 1
  4 ns: 1 1
  6 ns: 0 1
  8 ns: 0 1
  10 ns: 0 1
  FF::proc() in   val: 0
  FF::proc() out  val: 1
  12 ns: 1 0
  14 ns: 1 0
  16 ns: 0 0
  18 ns: 0 0
  20 ns: 0 0

!2007-04-02 Mon

SC_CTHREAD

2007-04-01 Sun との相違

  ***************
  *** 14,31 ****
    
      SC_CTOR(FF)
      {
  !     val = true;
  !     SC_METHOD(proc);
  !     sensitive << CLK.pos();
      }
    };
    
    void FF::proc(void)
    {
  !   cout << "FF::proc() in   val: " << val << endl;
  !   out.write(val);
  !   val = !val;
  !   cout << "FF::proc() out  val: " << val << endl;
    }
    
    int sc_main(int argc, char *argv[])
  --- 14,34 ----
    
      SC_CTOR(FF)
      {
  !     SC_CTHREAD(proc, CLK.pos());
      }
    };
    
    void FF::proc(void)
    {
  !   val = true;
  ! 
  !   while (1) {
  !     cout << "FF::proc() in   val: " << val << endl;
  !     out.write(val);
  !     val = !val;
  !     cout << "FF::proc() out  val: " << val << endl;
  !     wait();
  !   }
    }
    
    int sc_main(int argc, char *argv[])
で、
  FF::proc() in   val: 1
  FF::proc() out  val: 0
  0 s: 1 1
  2 ns: 1 1
  4 ns: 1 1
  6 ns: 0 1
  8 ns: 0 1
  10 ns: 0 1
  FF::proc() in   val: 0
  FF::proc() out  val: 1
  12 ns: 1 0
  14 ns: 1 0
  16 ns: 0 0
  18 ns: 0 0
  20 ns: 0 0

!2007-04-01 Sun

SC_CTOR 内で初期化

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FF)
  {
    sc_in_clk    CLK;
    sc_out<bool> out;
    bool val;
  
    void proc(void);
  
    SC_CTOR(FF)
    {
      val = true;
      SC_METHOD(proc);
      sensitive << CLK.pos();
    }
  };
  
  void FF::proc(void)
  {
    cout << "FF::proc() in   val: " << val << endl;
    out.write(val);
    val = !val;
    cout << "FF::proc() out  val: " << val << endl;
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS);
    sc_signal<bool> out;
  
    FF ff("FF");
    ff(Clk, out);
  
    sc_initialize();
  
    cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
  
    for (int i = 0; i < 5; i++) {
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
  
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << out << endl;
    }
  
    return 0;
  }
で、
  FF::proc() in   val: 1
  FF::proc() out  val: 0
  FF::proc() in   val: 0
  FF::proc() out  val: 1
  0 s: 1 0
  2 ns: 1 0
  4 ns: 1 0
  6 ns: 0 0
  8 ns: 0 0
  10 ns: 0 0
  FF::proc() in   val: 1
  FF::proc() out  val: 0
  12 ns: 1 1
  14 ns: 1 1
  16 ns: 0 1
  18 ns: 0 1
  20 ns: 0 1

* うーん、これで良いの？
* なぜ最初に FF::proc() が二度呼ばれる？
* SC_MODULE の中のクロック信号は sc_in_clk でなくて sc_in でも良いのか？？？

!2007-03-31 Sat

2007-03-20 Tue 複数モジュールを new を使わず記述

  ***************
  *** 31,46 ****
      sc_signal<bool> tmp;
      void buf(void);
    
  !   buffer *b1;
  !   buffer *b2;
    
  !   SC_CTOR(buffer2)
      {
  !     b1 = new buffer("b1");
  !     (*b1)(in, tmp);
  !     b2 = new buffer("b2");
  !     b2->in(tmp);
  !     b2->out(out);
    
        SC_METHOD(buf);
        sensitive << tmp;
  --- 31,49 ----
      sc_signal<bool> tmp;
      void buf(void);
    
  !   buffer b1;
  !   buffer b2;
    
  !   SC_CTOR(buffer2):
  !     in ("in"),
  !     out("out"),
  !     b1("b1"),
  !     b2("b2")
      {
  !     b1.in(in);
  !     b1.out(tmp);
  !     b2.in(tmp);
  !     b2.out(out);
    
        SC_METHOD(buf);
        sensitive << tmp;
という違いで、
  1 1
  0 0

!2007-03-30 Fri

sc_fifo, nb_{write,read}

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FIFOs)
  {
    sc_fifo_out<bool> out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    bool x = true;
  
    for (int i = 0; i < 10; i++) {
      out->nb_write(x);
      cout << "i : " << i << "  out : " << x << endl;
      x = !x;
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_fifo_in<bool> in;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOr)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    bool b;
  
    while (1) {
      cout << "in : " << in->nb_read(b) << endl;
      cout << "b  : " << b << endl;
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_fifo<bool> fifo;
  
    FIFOs fs("FIFOs");
    FIFOr fr("FIFOr");
    fs.out(fifo);
    fr.in(fifo);
  
    sc_initialize();
  
    return 0;
  }
で、
  i : 0  out : 1
  i : 1  out : 0
  i : 2  out : 1
  i : 3  out : 0
  i : 4  out : 1
  i : 5  out : 0
  i : 6  out : 1
  i : 7  out : 0
  i : 8  out : 1
  i : 9  out : 0
  in : 0
  b  : 0
  in : 0
  b  : 0
  in : 0
  b  : 0
  in : 0
  b  : 0
    ...

* 止まらない〜。多分、使い方間違ってる…

以下のように変更
  ***************
  *** 41,51 ****
    
    void FIFOr::FIFO_proc(void)
    {
  !   bool b;
    
      while (1) {
  !     cout << "in : " << in->nb_read(b) << endl;
  !     cout << "b  : " << b << endl;
      }
    }
    
  --- 41,52 ----
    
    void FIFOr::FIFO_proc(void)
    {
  !   //bool b;
    
      while (1) {
  !     //cout << "in : " << in->nb_read(b) << endl;
  !     cout << "in : " << in->read() << endl;
  !     //cout << "b  : " << b << endl;
      }
    }
    
で、
  i : 0  out : 1
  i : 1  out : 0
  i : 2  out : 1
  i : 3  out : 0
  i : 4  out : 1
  i : 5  out : 0
  i : 6  out : 1
  i : 7  out : 0
  i : 8  out : 1
  i : 9  out : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 

!2007-03-29 Thu

sc_fifo, num_free()

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FIFOs)
  {
    sc_fifo_out<bool> out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    bool x = true;
  
    for (int i = 0; i < 10; i++) {
      out->write(x);
      cout << "i : " << i << "  out : " << x << "  num : " << out->num_free() << endl;
      x = !x;
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_fifo_in<bool> in;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOr)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    while (1) {
      cout << "in : " << in->read() << endl;
      //cout << "in : " << in->read() << "  num : " << in->num_free() << endl;
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_fifo<bool> fifo;
  
    FIFOs fs("FIFOs");
    FIFOr fr("FIFOr");
    fs.out(fifo);
    fr.in(fifo);
  
    sc_initialize();
  
    return 0;
  }
で、
  i : 0  out : 1  num : 15
  i : 1  out : 0  num : 14
  i : 2  out : 1  num : 13
  i : 3  out : 0  num : 12
  i : 4  out : 1  num : 11
  i : 5  out : 0  num : 10
  i : 6  out : 1  num : 9
  i : 7  out : 0  num : 8
  i : 8  out : 1  num : 7
  i : 9  out : 0  num : 6
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 

!2007-03-28 Wed

sc_fifo, num_available()

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FIFOs)
  {
    sc_fifo_out<bool> out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    bool x = true;
  
    for (int i = 0; i < 10; i++) {
      out->write(x);
      cout << "i : " << i << "  out : " << x << endl;
      //cout << "i : " << i << "  out : " << x << "  num : " << out->num_available() << endl;
      x = !x;
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_fifo_in<bool> in;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOr)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    while (1) {
      cout << "in : " << in->read() << "  num : " << in->num_available() << endl;
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_fifo<bool> fifo;
  
    FIFOs fs("FIFOs");
    FIFOr fr("FIFOr");
    fs.out(fifo);
    fr.in(fifo);
  
    sc_initialize();
  
    return 0;
  }
で、
  i : 0  out : 1
  i : 1  out : 0
  i : 2  out : 1
  i : 3  out : 0
  i : 4  out : 1
  i : 5  out : 0
  i : 6  out : 1
  i : 7  out : 0
  i : 8  out : 1
  i : 9  out : 0
  in : 1  num : 0
  in : 0  num : 9
  in : 1  num : 8
  in : 0  num : 7
  in : 1  num : 6
  in : 0  num : 5
  in : 1  num : 4
  in : 0  num : 3
  in : 1  num : 2
  in : 0  num : 1
  in : 

!2007-03-27 Tue

sc_fifo

2007-03-24 Sat で、
  ***************
  *** 22,28 ****
    
      for (int i = 0; i < 10; i++) {
        out->write(x);
  !     cout << "i : " << i << "  out : " << x << endl;
        x = !x;
      }
    }
  --- 22,29 ----
    
      for (int i = 0; i < 10; i++) {
        out->write(x);
  !     cout << sc_time_stamp() << ":  i : " << i << "  out : " << x << endl;
  !     wait(1, SC_NS);
        x = !x;
      }
    }
  ***************
  *** 42,48 ****
    void FIFOr::FIFO_proc(void)
    {
      while (1) {
  !     cout << "in : " << in->read() << endl;
      }
    }
    
  --- 43,49 ----
    void FIFOr::FIFO_proc(void)
    {
      while (1) {
  !     cout << sc_time_stamp() << ":  in : " << in->read() << endl;
      }
    }
とすると、
  0 s:  i : 0  out : 1
  0 s:  in : 1
  0 s:  in : 
あれ？

さらに、
  ***************
  *** 57,62 ****
  --- 57,63 ----
      fr.in(fifo);
    
      sc_initialize();
  +   sc_start(20, SC_NS);
    
      return 0;
    }
とすると、
  0 s:  i : 0  out : 1
  0 s:  in : 1
  0 s:  in : 1 ns:  i : 1  out : 0
  0
  1 ns:  in : 2 ns:  i : 2  out : 1
  1
  2 ns:  in : 3 ns:  i : 3  out : 0
  0
  3 ns:  in : 4 ns:  i : 4  out : 1
  1
  4 ns:  in : 5 ns:  i : 5  out : 0
  0
  5 ns:  in : 6 ns:  i : 6  out : 1
  1
  6 ns:  in : 7 ns:  i : 7  out : 0
  0
  7 ns:  in : 8 ns:  i : 8  out : 1
  1
  8 ns:  in : 9 ns:  i : 9  out : 0
  0
  9 ns:  in : 

* 「sc_initialize();」は不要なのかも
* 「sc_start(-1);」でも最後まで実行してから終了した

!2007-03-26 Mon

sc_fifo

2007-03-24 Sat で、
  ***************
  *** 23,28 ****
  --- 23,29 ----
      for (int i = 0; i < 10; i++) {
        out->write(x);
        cout << "i : " << i << "  out : " << x << endl;
  +     wait(SC_ZERO_TIME);
        x = !x;
      }
    }
とすると、
  i : 0  out : 1
  in : 1
  in : i : 1  out : 0
  0
  in : i : 2  out : 1
  1
  in : i : 3  out : 0
  0
  in : i : 4  out : 1
  1
  in : i : 5  out : 0
  0
  in : i : 6  out : 1
  1
  in : i : 7  out : 0
  0
  in : i : 8  out : 1
  1
  in : i : 9  out : 0
  0
  in : 

うーん、なんで出力がこういう風に混ざっちゃうんだろう？

!2007-03-25 Sun

sc_fifo

2007-03-24 Sat で、
  ***************
  *** 48,54 ****
    
    int sc_main(int argc, char *argv[])
    {
  !   sc_fifo<bool> fifo;
    
      FIFOs fs("FIFOs");
      FIFOr fr("FIFOr");
  --- 48,54 ----
    
    int sc_main(int argc, char *argv[])
    {
  !   sc_fifo<bool> fifo(5);
    
      FIFOs fs("FIFOs");
      FIFOr fr("FIFOr");
とすると、
  i : 0  out : 1
  i : 1  out : 0
  i : 2  out : 1
  i : 3  out : 0
  i : 4  out : 1
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : i : 5  out : 0
  i : 6  out : 1
  i : 7  out : 0
  i : 8  out : 1
  i : 9  out : 0
  0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 

!2007-03-24 Sat

sc_fifo

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(FIFOs)
  {
    sc_fifo_out<bool> out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOs)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOs::FIFO_proc(void)
  {
    bool x = true;
  
    for (int i = 0; i < 10; i++) {
      out->write(x);
      cout << "i : " << i << "  out : " << x << endl;
      x = !x;
    }
  }
  
  SC_MODULE(FIFOr)
  {
    sc_fifo_in<bool> in;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFOr)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFOr::FIFO_proc(void)
  {
    while (1) {
      cout << "in : " << in->read() << endl;
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_fifo<bool> fifo;
  
    FIFOs fs("FIFOs");
    FIFOr fr("FIFOr");
    fs.out(fifo);
    fr.in(fifo);
  
    sc_initialize();
  
    return 0;
  }
で、
  i : 0  out : 1
  i : 1  out : 0
  i : 2  out : 1
  i : 3  out : 0
  i : 4  out : 1
  i : 5  out : 0
  i : 6  out : 1
  i : 7  out : 0
  i : 8  out : 1
  i : 9  out : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 1
  in : 0
  in : 

うーむ、良いのだろうか？

!2007-03-23 Fri

sc_fifo

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in, bool out)
  {
    //cout << sc_time_stamp() << ": " << in << " " << " " << out << endl;
    cout << in << " " << " " << out << endl;
  }
  
  SC_MODULE(FIFO)
  {
    sc_fifo_in <bool> in;
    sc_fifo_out<bool> out;
  
    void FIFO_proc(void);
  
    SC_CTOR(FIFO)
    {
      SC_THREAD(FIFO_proc);
    }
  };
  
  void FIFO::FIFO_proc(void)
  {
    while (1) {
      out.write(in.read());
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_fifo<bool> in;
    sc_fifo<bool> out;
  
    FIFO f("FIFO");
    f(in, out);
  
    sc_initialize();
    //sc_start();
  
    in = false;
    //output(in, out);
    //sc_start(1, SC_NS);
  
    in = true;
    //output(in, out);
    //sc_start(1, SC_NS);
  
    //output(in, out);
  
    return 0;
  }

値を出力しようとすると、以下のエラー。
おそらくすごい間違いをしているに違いない…
  Error: (E519) wait() is only allowed in SC_THREADs and SC_CTHREADs: 
          in SC_METHODs use next_trigger() instead
  In file: ../../../../src/systemc/kernel/sc_wait.cpp:88

!2007-03-22 Thu

2007-01-06 で sc_signal を sc_buffer に

で、
  1 1
  0 0

!2007-03-21 Wed

sc_simulation_time()

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << sc_simulation_time() << " " << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << sc_simulation_time() << " " << in << " " << out << endl;
  
    in = true;  sc_start(1, SC_NS);
    cout << sc_simulation_time() << " " << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << sc_simulation_time() << " " << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1 1
  2 0 0
  3 1 1
  4 0 0

!2007-03-20 Tue

複数モジュール

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  SC_MODULE(buffer2)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    sc_signal<bool> tmp;
    void buf(void);
  
    buffer *b1;
    buffer *b2;
  
    SC_CTOR(buffer2)
    {
      b1 = new buffer("b1");
      (*b1)(in, tmp);
      b2 = new buffer("b2");
      b2->in(tmp);
      b2->out(out);
  
      SC_METHOD(buf);
      sensitive << tmp;
    }
  };
  
  void buffer2::buf(void)
  {
    out.write(tmp.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer2 b("buffer");
    b(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1
  0 0

こんなんで良い？

!2007-03-19 Mon

new でインスタンス化とポート接続
(2007-01-13 Sat の形式を変えたもの)

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> IN;
    sc_signal<bool> OUT;
    buffer *b1;
  
    b1 = new buffer("buffer");
    b1->in(IN);
    b1->out(OUT);
  
    sc_initialize();
  
    IN = true;  sc_start(1, SC_NS);
    cout << IN << " " << OUT << endl;
  
    IN = false; sc_start(1, SC_NS);
    cout << IN << " " << OUT << endl;
  
    return 0;
  }
で、
  1 1
  0 0

!2007-03-18 Sun

notify_delayed()

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in1, bool in2, bool sel, bool out)
  {
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
  }
  
  SC_MODULE(SEL)
  {
    sc_in <bool> in1;
    sc_in <bool> in2;
    sc_in <bool> sel;
    sc_out<bool> out;
  
    sc_event sel1, sel2;
  
    void proc_sel(void);
    void proc1(void);
    void proc2(void);
  
    SC_CTOR(SEL)
    {
      SC_THREAD(proc_sel);
      sensitive << in1 << in2 << sel;
      SC_THREAD(proc1);
      SC_THREAD(proc2);
    }
  };
  
  void SEL::proc_sel(void)
  {
    while (1) {
      wait();
      if (sel.read()) {
        sel1.notify_delayed();
      } else {
        sel2.notify_delayed();
      }
    }
  }
  
  void SEL::proc1(void)
  {
    while (1) {
      wait(sel1);
      out.write(in1.read());
    }
  }
  
  void SEL::proc2(void)
  {
    while (1) {
      wait(sel2);
      out.write(in2.read());
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2, sel;
    sc_signal<bool> out;
  
    SEL sel2("SEL");
    sel2(in1, in2, sel, out);
  
    sc_initialize();
  
    in1 = false; in2 = true; sel = true;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    in1 = true; in2 = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    sel = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    return 0;
  }
で、
  0 s: 0 0 0 0
  1 ns: 0 1 1 0
  2 ns: 0 1 1 0
  3 ns: 0 1 1 0
  4 ns: 0 1 1 0
  5 ns: 0 1 1 0
  6 ns: 1 0 1 1
  7 ns: 1 0 1 1
  8 ns: 1 0 1 1
  9 ns: 1 0 1 1
  10 ns: 1 0 1 1
  11 ns: 1 0 0 0
  12 ns: 1 0 0 0
  13 ns: 1 0 0 0
  14 ns: 1 0 0 0

遅延はなし(delta)ってこと？？？

!2007-03-17 Sat

cancel()

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in1, bool in2, bool sel, bool out)
  {
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
  }
  
  SC_MODULE(SEL)
  {
    sc_in <bool> in1;
    sc_in <bool> in2;
    sc_in <bool> sel;
    sc_out<bool> out;
  
    sc_event sel1, sel2;
  
    void proc_sel(void);
    void proc1(void);
    void proc2(void);
  
    SC_CTOR(SEL)
    {
      SC_THREAD(proc_sel);
      sensitive << in1 << in2 << sel;
      SC_THREAD(proc1);
      SC_THREAD(proc2);
    }
  };
  
  void SEL::proc_sel(void)
  {
    while (1) {
      wait();
      if (sel.read()) {
        //sel1.notify();
        sel1.notify_delayed(3, SC_NS);
        sel1.cancel();
      } else {
        //sel2.notify();
        sel2.notify_delayed(3, SC_NS);
      }
    }
  }
  
  void SEL::proc1(void)
  {
    while (1) {
      wait(sel1);
      out.write(in1.read());
    }
  }
  
  void SEL::proc2(void)
  {
    while (1) {
      wait(sel2);
      out.write(in2.read());
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2, sel;
    sc_signal<bool> out;
  
    SEL sel2("SEL");
    sel2(in1, in2, sel, out);
  
    sc_initialize();
  
    in1 = false; in2 = true; sel = true;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    in1 = true; in2 = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    sel = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    sel = true;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    return 0;
  }
で、
  0 s: 0 0 0 0
  1 ns: 0 1 1 0
  2 ns: 0 1 1 0
  3 ns: 0 1 1 0
  4 ns: 0 1 1 0
  5 ns: 0 1 1 0
  6 ns: 1 0 1 0
  7 ns: 1 0 1 0
  8 ns: 1 0 1 0
  9 ns: 1 0 1 0
  10 ns: 1 0 1 0
  11 ns: 1 0 0 0
  12 ns: 1 0 0 0
  13 ns: 1 0 0 0
  14 ns: 1 0 0 0
  15 ns: 1 0 0 0
  16 ns: 1 0 1 0
  17 ns: 1 0 1 0
  18 ns: 1 0 1 0
  19 ns: 1 0 1 0
？

!2007-03-16 Fri

notify_delayed()

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in1, bool in2, bool sel, bool out)
  {
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
  }
  
  SC_MODULE(SEL)
  {
    sc_in <bool> in1;
    sc_in <bool> in2;
    sc_in <bool> sel;
    sc_out<bool> out;
  
    sc_event sel1, sel2;
  
    void proc_sel(void);
    void proc1(void);
    void proc2(void);
  
    SC_CTOR(SEL)
    {
      SC_THREAD(proc_sel);
      sensitive << in1 << in2 << sel;
      SC_THREAD(proc1);
      SC_THREAD(proc2);
    }
  };
  
  void SEL::proc_sel(void)
  {
    while (1) {
      wait();
      if (sel.read()) {
        sel1.notify_delayed(3, SC_NS);
      } else {
        sel2.notify_delayed(3, SC_NS);
      }
    }
  }
  
  void SEL::proc1(void)
  {
    while (1) {
      wait(sel1);
      out.write(in1.read());
    }
  }
  
  void SEL::proc2(void)
  {
    while (1) {
      wait(sel2);
      out.write(in2.read());
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2, sel;
    sc_signal<bool> out;
  
    SEL sel2("SEL");
    sel2(in1, in2, sel, out);
  
    sc_initialize();
  
    in1 = false; in2 = true; sel = true;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    in1 = true; in2 = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    sel = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    return 0;
  }
で、
  0 s: 0 0 0 0
  1 ns: 0 1 1 0
  2 ns: 0 1 1 0
  3 ns: 0 1 1 0
  4 ns: 0 1 1 0
  5 ns: 0 1 1 0
  6 ns: 1 0 1 0
  7 ns: 1 0 1 0
  8 ns: 1 0 1 0
  9 ns: 1 0 1 1
  10 ns: 1 0 1 1
  11 ns: 1 0 0 1
  12 ns: 1 0 0 1
  13 ns: 1 0 0 1
  14 ns: 1 0 0 0

時間単位不要と書かれた本にだまされた…

!2007-03-15 Thu

SC_THREAD, wait(n, UNIT, event);

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in1, bool in2, bool sel, bool out)
  {
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
  }
  
  SC_MODULE(SEL)
  {
    sc_in <bool> in1;
    sc_in <bool> in2;
    sc_in <bool> sel;
    sc_out<bool> out;
  
    sc_event sel1, sel2;
  
    void proc_sel(void);
    void proc1(void);
    void proc2(void);
  
    SC_CTOR(SEL)
    {
      SC_THREAD(proc_sel);
      sensitive << in1 << in2 << sel;
      SC_THREAD(proc1);
      SC_THREAD(proc2);
    }
  };
  
  void SEL::proc_sel(void)
  {
    while (1) {
      wait();
      if (sel.read()) {
        sel1.notify();
      } else {
        sel2.notify();
      }
    }
  }
  
  void SEL::proc1(void)
  {
    while (1) {
      wait(3, SC_NS, sel1);
      out.write(in1.read());
    }
  }
  
  void SEL::proc2(void)
  {
    while (1) {
      wait(3, SC_NS, sel2);
      out.write(in2.read());
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2, sel;
    sc_signal<bool> out;
  
    SEL sel2("SEL");
    sel2(in1, in2, sel, out);
  
    sc_initialize();
  
    in1 = false; in2 = true; sel = true;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    in1 = true; in2 = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    sel = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    return 0;
  }
で、
  0 s: 0 0 0 0
  1 ns: 0 1 1 0
  2 ns: 0 1 1 0
  3 ns: 0 1 1 0
  4 ns: 0 1 1 0
  5 ns: 0 1 1 0
  6 ns: 1 0 1 1
  7 ns: 1 0 1 0
  8 ns: 1 0 1 0
  9 ns: 1 0 1 1
  10 ns: 1 0 1 0
  11 ns: 1 0 0 0
  12 ns: 1 0 0 1
  13 ns: 1 0 0 1
  14 ns: 1 0 0 0

？

!2007-03-14 Wed

SC_THREAD, wait(n, UNIT);

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in1, bool in2, bool sel, bool out)
  {
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
  }
  
  SC_MODULE(SEL)
  {
    sc_in <bool> in1;
    sc_in <bool> in2;
    sc_in <bool> sel;
    sc_out<bool> out;
  
    //sc_event sel1, sel2;
  
    void proc_sel(void);
    //void proc1(void);
    //void proc2(void);
  
    SC_CTOR(SEL)
    {
      SC_THREAD(proc_sel);
      sensitive << in1 << in2 << sel;
      //SC_THREAD(proc1);
      //SC_THREAD(proc2);
    }
  };
  
  void SEL::proc_sel(void)
  {
    while (1) {
      wait();
      wait(3, SC_NS);
      if (sel.read()) {
        out.write(in1.read());
      } else {
        out.write(in2.read());
      }
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2, sel;
    sc_signal<bool> out;
  
    SEL sel2("SEL");
    sel2(in1, in2, sel, out);
  
    sc_initialize();
  
    in1 = false; in2 = true; sel = true;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    in1 = true; in2 = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    sel = false;
    for (int i = 0; i < 5; i++) {output(in1, in2, sel, out); sc_start(1, SC_NS);}
  
    return 0;
  }
で、
  0 s: 0 0 0 0
  1 ns: 0 1 1 0
  2 ns: 0 1 1 0
  3 ns: 0 1 1 0
  4 ns: 0 1 1 0
  5 ns: 0 1 1 0
  6 ns: 1 0 1 0
  7 ns: 1 0 1 0
  8 ns: 1 0 1 0
  9 ns: 1 0 1 1
  10 ns: 1 0 1 1
  11 ns: 1 0 0 1
  12 ns: 1 0 0 1
  13 ns: 1 0 0 1
  14 ns: 1 0 0 0

!2007-03-13 Tue

SC_THREAD

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in1, bool in2, bool sel, bool out)
  {
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
  }
  
  SC_MODULE(SEL)
  {
    sc_in <bool> in1;
    sc_in <bool> in2;
    sc_in <bool> sel;
    sc_out<bool> out;
  
    //sc_event sel1, sel2;
  
    void proc_sel(void);
    //void proc1(void);
    //void proc2(void);
  
    SC_CTOR(SEL)
    {
      SC_THREAD(proc_sel);
      sensitive << in1 << in2 << sel;
      //SC_THREAD(proc1);
      //SC_THREAD(proc2);
    }
  };
  
  void SEL::proc_sel(void)
  {
    while (1) {
      wait();
      if (sel.read()) {
        out.write(in1.read());
      } else {
        out.write(in2.read());
      }
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2, sel;
    sc_signal<bool> out;
  
    SEL sel2("SEL");
    sel2(in1, in2, sel, out);
  
    sc_initialize();
  
    in1 = false; in2 = true; sel = true;
    output(in1, in2, sel, out);
    sc_start(1, SC_NS);
  
    in1 = true; in2 = false;
    output(in1, in2, sel, out);
    sc_start(1, SC_NS);
  
    sel = false;
    output(in1, in2, sel, out);
    sc_start(1, SC_NS);
  
    output(in1, in2, sel, out);
  
    return 0;
  }
で、
  0 s: 0 0 0 0
  1 ns: 0 1 1 0
  2 ns: 1 0 1 1
  3 ns: 1 0 0 0

嬉しい？

!2007-03-12 Mon

出力処理を関数化

  #include <iostream>
  #include "systemc.h"
  
  static void output(bool in, bool out)
  {
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  }
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    output(in, out);
  
    in = false; sc_start(1, SC_NS);
    output(in, out);
  
    return 0;
  }
で、
  1 ns: 1 1
  2 ns: 0 0

!2007-03-11 Sun

SC_THREAD

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(SEL)
  {
    sc_in <bool> in1;
    sc_in <bool> in2;
    sc_in <bool> sel;
    sc_out<bool> out;
  
    sc_event sel1, sel2;
  
    void proc_sel(void);
    void proc1(void);
    void proc2(void);
  
    SC_CTOR(SEL)
    {
      SC_THREAD(proc_sel);
      sensitive << in1 << in2 << sel;
      SC_THREAD(proc1);
      SC_THREAD(proc2);
    }
  };
  
  void SEL::proc_sel(void)
  {
    while (1) {
      wait();
      if (sel.read()) {
        sel1.notify();
      } else {
        sel2.notify();
      }
    }
  }
  
  void SEL::proc1(void)
  {
    while (1) {
      wait(sel1);
      out.write(in1.read());
    }
  }
  
  void SEL::proc2(void)
  {
    while (1) {
      wait(sel2);
      out.write(in2.read());
    }
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2, sel;
    sc_signal<bool> out;
  
    SEL sel2("SEL");
    sel2(in1, in2, sel, out);
  
    sc_initialize();
  
    in1 = false; in2 = true; sel = true;
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
    sc_start(1, SC_NS);
  
    in1 = true; in2 = false;
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
    sc_start(1, SC_NS);
  
    sel = false;
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
    sc_start(1, SC_NS);
  
    cout << sc_time_stamp() << ": " << in1 << " " << in2 << " "
         << sel << " " << out << endl;
  
    return 0;
  }
で、
  0 s: 0 0 0 0
  1 ns: 0 1 1 0
  2 ns: 1 0 1 1
  3 ns: 1 0 0 0

!2007-03-10 Sat

しつこく信号更新タイミングとかチェック

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(DFF)
  {
    sc_in_clk    CLK;
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void proc(void);
  
    SC_CTOR(DFF)
    {
      SC_METHOD(proc);
      sensitive << CLK.pos();
    }
  };
  
  void DFF::proc(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk1", 20, SC_NS);
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    DFF dff("DFF");
    dff(Clk, in, out);
  
    sc_initialize();
  
    in = false;
    cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
  
    sc_start(1, SC_NS);
  
    for (int i = 0; i < 5; i++) {
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
      sc_start(8, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
      sc_start(1, SC_NS);
      if (i % 3 != 0) in = !in;
  
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
      sc_start(1, SC_NS);
    }
  
    return 0;
  }
で、
  0 s: 1 0 0
  1 ns: 1 0 0
  9 ns: 1 0 0
  10 ns: 1 0 0
  11 ns: 0 0 0
  19 ns: 0 0 0
  20 ns: 0 0 0
  21 ns: 1 1 1
  29 ns: 1 1 1
  30 ns: 1 1 1
  31 ns: 0 0 1
  39 ns: 0 0 1
  40 ns: 0 0 1
  41 ns: 1 0 0
  49 ns: 1 0 0
  50 ns: 1 0 0

!2007-03-09 Fri

しつこく信号更新タイミングとかチェック

  #include <iostream>
  #include "systemc.h"
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk1", 4, SC_NS);
    sc_signal<bool> in;
  
    sc_initialize();
  
    in = false;
    cout << sc_time_stamp() << ": " << Clk << " " << in << endl;
  
    sc_start(0.1, SC_NS);
  
    for (int i = 0; i < 5; i++) {
      cout << sc_time_stamp() << ": " << Clk << " " << in << endl;
      sc_start(0.8, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << endl;
      sc_start(0.1, SC_NS);
      in = !in;
  
      cout << sc_time_stamp() << ": " << Clk << " " << in << endl;
      sc_start(0.1, SC_NS);
    }
  
    return 0;
  }
で、
  0 s: 1 0
  100 ps: 1 0
  900 ps: 1 0
  1 ns: 1 0
  1100 ps: 1 1
  1900 ps: 1 1
  2 ns: 1 1
  2100 ps: 0 0
  2900 ps: 0 0
  3 ns: 0 0
  3100 ps: 0 1
  3900 ps: 0 1
  4 ns: 0 1
  4100 ps: 1 0
  4900 ps: 1 0
  5 ns: 1 0

!2007-03-08 Thu

しつこく信号更新タイミングとかチェック

  #include <iostream>
  #include "systemc.h"
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk1", 4, SC_NS);
  
    sc_initialize();
  
    cout << sc_time_stamp() << ": " << Clk << endl;
    sc_start(0.1, SC_NS);
  
    for (int i = 0; i < 5; i++) {
      cout << sc_time_stamp() << ": " << Clk << endl;
      sc_start(0.8, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << endl;
      sc_start(0.1, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << endl;
      sc_start(0.1, SC_NS);
    }
  
    return 0;
  }
で、
  0 s: 1
  100 ps: 1
  900 ps: 1
  1 ns: 1
  1100 ps: 1
  1900 ps: 1
  2 ns: 1
  2100 ps: 0
  2900 ps: 0
  3 ns: 0
  3100 ps: 0
  3900 ps: 0
  4 ns: 0
  4100 ps: 1
  4900 ps: 1
  5 ns: 1

!2007-03-07 Wed

ちょっと信号更新タイミングとかチェック

  #include <iostream>
  #include "systemc.h"
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
  
    sc_initialize();
  
    cout << sc_time_stamp() << ": " << in << endl;
    in = false;
    cout << sc_time_stamp() << ": " << in << endl;
    in = true;
    cout << sc_time_stamp() << ": " << in << endl;
    sc_start(1, SC_NS);
    cout << sc_time_stamp() << ": " << in << endl;
    in = false;
    cout << sc_time_stamp() << ": " << in << endl;
    sc_start(1, SC_NS);
    cout << sc_time_stamp() << ": " << in << endl;
    sc_start(1, SC_NS);
    cout << sc_time_stamp() << ": " << in << endl;
  
    return 0;
  }
で、
  0 s: 0
  0 s: 0
  0 s: 0
  1 ns: 1
  1 ns: 1
  2 ns: 0
  3 ns: 0

!2007-03-06 Tue

ちょっと信号更新タイミングとかチェック

  #include <iostream>
  #include "systemc.h"
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk1", 10, SC_NS);
    sc_signal<bool> in;
  
    sc_initialize();
  
    in = false;
  
    for (int i = 0; i < 10; i++) {
      cout << sc_time_stamp() << ": " << Clk << " " << in << endl;
      sc_start(1, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << endl;
  
      in = !in;
    }
  
    return 0;
  }
で、
  0 s: 1 0
  1 ns: 1 0
  1 ns: 1 0
  2 ns: 1 1
  2 ns: 1 1
  3 ns: 1 0
  3 ns: 1 0
  4 ns: 1 1
  4 ns: 1 1
  5 ns: 1 0
  5 ns: 1 0
  6 ns: 0 1
  6 ns: 0 1
  7 ns: 0 0
  7 ns: 0 0
  8 ns: 0 1
  8 ns: 0 1
  9 ns: 0 0
  9 ns: 0 0
  10 ns: 0 1

!2007-03-05 Mon

一番簡単な sc_clock

  #include <iostream>
  #include "systemc.h"
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk1", 10, SC_NS);
  
    sc_initialize();
  
    for (int i = 0; i < 15; i++) {
      cout << sc_time_stamp() << ": " << Clk << endl;
      sc_start(1, SC_NS);
    }
  
    return 0;
  }
で、
  0 s: 1
  1 ns: 1
  2 ns: 1
  3 ns: 1
  4 ns: 1
  5 ns: 1
  6 ns: 0
  7 ns: 0
  8 ns: 0
  9 ns: 0
  10 ns: 0
  11 ns: 1
  12 ns: 1
  13 ns: 1
  14 ns: 1

それにしても、display 文みたいなものはないのかな？
しょせん C++ のライブラリだから監視用プロセスのようなものを作らないと無理？？？

!2007-03-04 Sun

sensitive_pos

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(DFF)
  {
    sc_in_clk    CLK;
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void proc(void);
  
    SC_CTOR(DFF)
    {
      SC_METHOD(proc);
      sensitive_pos << CLK;
    }
  };
  
  void DFF::proc(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS, 0.5, 0, SC_NS, false);
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    DFF dff("DFF");
    dff(Clk, in, out);
  
    sc_initialize();
  
    in = false;
  
    for (int i = 0; i < 10; i++) {
      sc_start(15, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
  
      in = !in;
    }
  
    return 0;
  }
で、
  15 ns: 0 0 0
  30 ns: 1 1 1
  45 ns: 0 0 0
  60 ns: 1 1 1
  75 ns: 0 0 0
  90 ns: 1 1 1
  105 ns: 0 0 0
  120 ns: 1 1 1
  135 ns: 0 0 0
  150 ns: 1 1 1

sensitive_neg もある

!2007-03-03 Sat

ビット幅のパラメータ化

  #include <iostream>
  #include "systemc.h"
  
  const int BITW = 4;
  
  SC_MODULE(DFF)
  {
    sc_in_clk    CLK;
    sc_in <sc_uint<BITW> > in;
    sc_out<sc_uint<BITW> > Q;
  
    void proc(void);
  
    SC_CTOR(DFF)
    {
      SC_METHOD(proc);
      sensitive << CLK.pos();
    }
  };
  
  void DFF::proc(void)
  {
    Q.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS, 0.5, 0, SC_NS, false);
    sc_signal<sc_uint<BITW> > in;
    sc_signal<sc_uint<BITW> > out;
    sc_uint<BITW> cnt = 1;
  
    DFF dff("DFF");
    dff(Clk, in, out);
  
    sc_initialize();
  
    in = cnt;
  
    cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
  
    for (int i = 0; i < 5; i++) {
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
  
      in = cnt++; sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
    }
  
    return 0;
  }
で、
  0 s: 0 0 0
  2 ns: 0 1 0
  4 ns: 0 1 0
  6 ns: 1 1 1
  8 ns: 1 2 1
  10 ns: 1 2 1
  12 ns: 0 3 1
  14 ns: 0 3 1
  16 ns: 1 4 4
  18 ns: 1 4 4
  20 ns: 1 5 4

const をはずすとダメ。って、明らかに C++ の仕様だよな

!2007-03-02 Fri

2007-03-01 のコードで「Q_.write(!Q);」を「Q_ = !Q;」に

  0 s: 0 0 0 1
  2 ns: 0 0 0 1
  4 ns: 0 1 0 1
  6 ns: 1 1 1 0
  8 ns: 1 0 1 0
  10 ns: 1 0 1 0
  12 ns: 0 1 1 0
  14 ns: 0 1 1 0
  16 ns: 1 0 0 1
  18 ns: 1 0 0 1
  20 ns: 1 1 0 1

うーん、「=」が「write」に割り当てられているのじゃないかという疑惑。
チェックしてみる

include/systemc/communication/sc_signal_ports.h
      this_type& operator = ( const this_type& port_ )
  	{ (*this)->write( port_->read() ); return *this; }

!2007-03-01 Thu

DFF Q の反転出力もつける

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(DFF)
  {
    sc_in_clk    CLK;
    sc_in <bool>  in;
    sc_out<bool> Q;
    sc_out<bool> Q_;
  
    void proc1(void);
    void proc2(void);
  
    SC_CTOR(DFF)
    {
      SC_METHOD(proc1);
      sensitive << CLK.pos();
      SC_METHOD(proc2);
      sensitive << Q;
    }
  };
  
  void DFF::proc1(void)
  {
    Q.write(in.read());
  }
  
  void DFF::proc2(void)
  {
    Q_.write(!Q);
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS, 0.5, 0, SC_NS, false);
    sc_signal<bool> in;
    sc_signal<bool> q, q_;
  
    DFF dff("DFF");
    dff(Clk, in, q, q_);
  
    sc_initialize();
  
    in = false;
  
    cout << sc_time_stamp() << ": " << Clk << " " << in << " " << q << " " << q_ << endl;
  
    for (int i = 0; i < 5; i++) {
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << q << " " << q_ << endl;
  
      in = !in; sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << q << " " << q_ << endl;
    }
  
    return 0;
  }
で、
  0 s: 0 0 0 1
  2 ns: 0 0 0 1
  4 ns: 0 1 0 1
  6 ns: 1 1 1 0
  8 ns: 1 0 1 0
  10 ns: 1 0 1 0
  12 ns: 0 1 1 0
  14 ns: 0 1 1 0
  16 ns: 1 0 0 1
  18 ns: 1 0 0 1
  20 ns: 1 1 0 1

!2007-02-28 Wed

2007-02-27 のコードで「CLK.pos()」を「CLK.neg()」に

  0 s: 1 0 0
  2 ns: 1 0 0
  4 ns: 1 1 0
  6 ns: 0 1 1
  8 ns: 0 0 1
  10 ns: 0 0 1
  12 ns: 1 1 1
  14 ns: 1 1 1
  16 ns: 0 0 0
  18 ns: 0 0 0
  20 ns: 0 1 0

!2007-02-27 Tue

sc_in_clk

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(DFF)
  {
    sc_in_clk    CLK;
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void proc(void);
  
    SC_CTOR(DFF)
    {
      SC_METHOD(proc);
      sensitive << CLK.pos();
    }
  };
  
  void DFF::proc(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_clock Clk("Clk", 10, SC_NS);
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    DFF dff("DFF");
    dff(Clk, in, out);
  
    sc_initialize();
  
    in = false;
  
    cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
  
    for (int i = 0; i < 5; i++) {
      sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
  
      in = !in; sc_start(2, SC_NS);
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
    }
  
    return 0;
  }
で、
  0 s: 1 0 0
  2 ns: 1 0 0
  4 ns: 1 1 0
  6 ns: 0 1 0
  8 ns: 0 0 0
  10 ns: 0 0 0
  12 ns: 1 1 1
  14 ns: 1 1 1
  16 ns: 0 0 1
  18 ns: 0 0 1
  20 ns: 0 1 1

波形で見ないと非常に分かりにくい…

!2007-02-26 Mon

sc_time

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_time t(1, SC_NS);
  
    sc_initialize();
  
    in = true;  sc_start(t);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    in = false; sc_start(t);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    return 0;
  }
で、
  1 ns: 1 1
  2 ns: 0 0

「sc_time t(1);」のように単位は省略できない？

!2007-02-25 Sun

sc_start(-1)

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(-1);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    in = false; sc_start(1);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    return 0;
  }
で、
  18446744073709551615 ps: 1 1
  999 ps: 0 0

うぴょ？

!2007-02-24 Sat

sc_start とかで単位なし

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    in = false; sc_start(1);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    return 0;
  }
で、
  1 ns: 1 1
  2 ns: 0 0

!2007-02-23 Fri

* sc_cycle って何なんだ？
* sc_initialize の alias なの？？？
* どうもそうではなさそう。でも、sc_start との差は？そもそも、sc_start っていう名前はちょっと意味不明なんだが… include/systemc/kernel/sc_simcontext.h 読めってか？

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
    sc_cycle(1, SC_NS);
  
    in = true;  sc_start(1, SC_NS);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << sc_time_stamp() << ": " << in << " " << out << endl;
  
    return 0;
  }
で、
  2 ns: 1 1
  3 ns: 0 0

!2007-02-22 Thu

sc_stop

2007-01-06 のコードで、sc_stop を挿入

    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    sc_stop();
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;

何も変わらないと思ったら、
  1 1
  1 1
と値が変わらなくなっていた

!2007-02-21 Wed

まだまだ sc_clock

2007-02-16 のコードで
  sc_clock Clk("Clk1", 10, SC_NS);
を
  sc_clock Clk("Clk1", 10, SC_NS, 0.2, 0, SC_NS, false);
にすると、
  0 s: 0 0 0
  1 ns: 0 1 1
  2 ns: 0 0 0
  3 ns: 0 1 1
  4 ns: 0 0 0
  5 ns: 0 1 1
  6 ns: 0 0 0
  7 ns: 0 1 1
  8 ns: 0 0 0
  9 ns: 1 1 1
  10 ns: 1 0 0
  11 ns: 0 1 1
  12 ns: 0 0 0
  13 ns: 0 1 1
  14 ns: 0 0 0
  15 ns: 0 1 1
  16 ns: 0 0 0
  17 ns: 0 1 1
  18 ns: 0 0 0
  19 ns: 1 1 1

!2007-02-20 Tue

まだまだ sc_clock

2007-02-16 のコードで
  sc_clock Clk("Clk1", 10, SC_NS);
を
  sc_clock Clk("Clk1", 10, SC_NS, 0.2, 5, SC_NS);
にすると、
  0 s: 0 0 0
  1 ns: 0 1 1
  2 ns: 0 0 0
  3 ns: 0 1 1
  4 ns: 0 0 0
  5 ns: 0 1 1
  6 ns: 1 0 0
  7 ns: 1 1 1
  8 ns: 0 0 0
  9 ns: 0 1 1
  10 ns: 0 0 0
  11 ns: 0 1 1
  12 ns: 0 0 0
  13 ns: 0 1 1
  14 ns: 0 0 0
  15 ns: 0 1 1
  16 ns: 1 0 0
  17 ns: 1 1 1
  18 ns: 0 0 0
  19 ns: 0 1 1

!2007-02-19 Mon

sc_clock に戻る

2007-02-16 のコードで
  sc_clock Clk("Clk1", 10, SC_NS);
を
  sc_clock Clk("Clk1", 10, SC_NS, 0.2);
にすると、
  0 s: 1 0 0
  1 ns: 1 1 1
  2 ns: 1 0 0
  3 ns: 0 1 1
  4 ns: 0 0 0
  5 ns: 0 1 1
  6 ns: 0 0 0
  7 ns: 0 1 1
  8 ns: 0 0 0
  9 ns: 0 1 1
  10 ns: 0 0 0
  11 ns: 1 1 1
  12 ns: 1 0 0
  13 ns: 0 1 1
  14 ns: 0 0 0
  15 ns: 0 1 1
  16 ns: 0 0 0
  17 ns: 0 1 1
  18 ns: 0 0 0
  19 ns: 0 1 1

!2007-02-18 Sun

2007-01-18 のコードで
  cout << in1 << " " << in2 << " " << out << endl;
を
  cout << setw(3) << in1 << " " << setw(3) << in2 << " " << setw(3) << out << endl;
に変更で(「#include <iomanip>」も追加)、出力が
  1 1 2
  255 255 510
から
    1   1   2
  255 255 510
に

!2007-02-17 Sat

2007-02-16 のコードで出力を
  cout << setw(2) << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
に変更(「#include <iomanip>」も追加)

結果変わらず…。まあそういうものかもしれない

「setw(2)」のせいか？と思ったので「setw(4)」にしても変わらず…

!2007-02-16 Fri

sc_clock

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
    sc_clock Clk("Clk1", 10, SC_NS);
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    for (int i = 0; i < 10; i++) {
      in = true;
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
      sc_start(1, SC_NS);
  
      in = false;
      cout << sc_time_stamp() << ": " << Clk << " " << in << " " << out << endl;
      sc_start(1, SC_NS);
    }
  
    return 0;
  }
で、
  0 s: 1 0 0
  1 ns: 1 1 1
  2 ns: 1 0 0
  3 ns: 1 1 1
  4 ns: 1 0 0
  5 ns: 1 1 1
  6 ns: 0 0 0
  7 ns: 0 1 1
  8 ns: 0 0 0
  9 ns: 0 1 1
  10 ns: 0 0 0
  11 ns: 1 1 1
  12 ns: 1 0 0
  13 ns: 1 1 1
  14 ns: 1 0 0
  15 ns: 1 1 1
  16 ns: 0 0 0
  17 ns: 0 1 1
  18 ns: 0 0 0
  19 ns: 0 1 1

!2007-02-15 Thu

ふと思った、クラス内(?)に書けるんじゃないの？

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    //void buf(void);
    void buf(void)
    {
      out.write(in.read());
    }
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1
  0 0

「-E」をつけてコンパイルもしてみた。
これだけでかいものをパーズするわけだから遅くなるわけだ…

!2007-02-14 Wed

型ふたたび

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Adder)
  {
    sc_in <int> in1, in2;
    sc_out<int> out;
  
    void add(void);
  
    SC_CTOR(Adder)
    {
      SC_METHOD(add);
      sensitive << in1 << in2;
    }
  };
  
  void Adder::add(void)
  {
    out.write(in1.read() + in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<int> in1, in2;
    sc_signal<int> out;
  
    Adder x("Adder");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 255; in2 = 255; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = -1; in2 = -1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  1 1 2
  255 255 510
  -1 -1 -2

「int」を「unsinged char」にすると変な値が出てくるぞ

!2007-02-13 Tue

中間変数

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Adder)
  {
    sc_in <sc_uint<8> > in1, in2;
    sc_out<sc_uint<9> > out;
  
    void add(void);
  
    SC_CTOR(Adder)
    {
      SC_METHOD(add);
      sensitive << in1 << in2;
    }
  };
  
  void Adder::add(void)
  {
    int i1 = in1.read();
    int i2 = in2.read();
  
    out.write(i1 + i2);
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in1, in2;
    sc_signal<sc_uint<9> > out;
  
    Adder x("Adder");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 255; in2 = 255; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  1 1 2
  255 255 510

int でも良いの？意味が良く分からん

!2007-02-12 Mon

「.read()」を使わないと？

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(AND)
  {
    sc_in <bool> in1, in2;
    sc_out<bool> out;
  
    void and(void);
  
    SC_CTOR(AND)
    {
      SC_METHOD(and);
      sensitive << in1 << in2;
    }
  };
  
  void AND::and(void)
  {
    out.write(in1 & in2);
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2;
    sc_signal<bool> out;
  
    AND x("and");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = false; in2 = false; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = false; in2 = true;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = true;  in2 = true;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  0 0 0
  0 1 0
  1 1 1

「+」とかの演算だとコンパイルエラー

!2007-02-11 Sun

「.read()」を使わないと？

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in);
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1
  0 0

ふむ、

!2007-02-10 Sat

sc_lv には + などの演算はない

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(AND)
  {
    sc_in <sc_lv<8> > in1, in2;
    sc_out<sc_lv<8> > out;
  
    void and(void);
  
    SC_CTOR(AND)
    {
      SC_METHOD(and);
      sensitive << in1 << in2;
    }
  };
  
  void AND::and(void)
  {
    sc_uint<8> u1, u2;
  
    u1 = in1.read();
    u2 = in2.read();
    out.write(u1 + u2);
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_lv<8> > in1, in2;
    sc_signal<sc_lv<8> > out;
  
    AND x("and");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 0; in2 = 0; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  
  Warning: (W212) sc_logic value 'X' cannot be converted to bool
  In file: ../../../../../src/systemc/datatypes/bit/sc_logic.cpp:85
  In process: and.and @ 0 s
  00000000 00000000 00000000

良く分からないな〜。どうしろと？

!2007-02-09 Fri

リダクション演算 XOR

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Test)
  {
    sc_in <sc_uint<8> > in;
    sc_out<bool> out;
  
    void test_proc(void);
  
    SC_CTOR(Test)
    {
      SC_METHOD(test_proc);
      sensitive << in;
    }
  };
  
  void Test::test_proc(void)
  {
    out.write(in.read().xor_reduce());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in;
    sc_signal<bool> out;
  
    Test x("Test");
    x(in, out);
  
    sc_initialize();
  
    in = 0x55; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = 0x00; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = 0x01; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  85 0
  0 0
  1 1

!2007-02-08 Thu

リダクション演算 OR

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Test)
  {
    sc_in <sc_uint<8> > in;
    sc_out<bool> out;
  
    void test_proc(void);
  
    SC_CTOR(Test)
    {
      SC_METHOD(test_proc);
      sensitive << in;
    }
  };
  
  void Test::test_proc(void)
  {
    out.write(in.read().or_reduce());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in;
    sc_signal<bool> out;
  
    Test x("Test");
    x(in, out);
  
    sc_initialize();
  
    in = 0x55; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = 0x00; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  85 1
  0 0

!2007-02-07 Wed

リダクション演算 AND

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Test)
  {
    sc_in <sc_uint<8> > in;
    sc_out<bool> out;
  
    void test_proc(void);
  
    SC_CTOR(Test)
    {
      SC_METHOD(test_proc);
      sensitive << in;
    }
  };
  
  void Test::test_proc(void)
  {
    out.write(in.read().and_reduce());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in;
    sc_signal<bool> out;
  
    Test x("Test");
    x(in, out);
  
    sc_initialize();
  
    in = 0x55; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = 0xff; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  85 0
  255 1

!2007-02-06 Tue

部分選択

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Range)
  {
    sc_in <sc_uint<8> > in;
    sc_out<sc_uint<8> > out;
  
    void range_proc(void);
  
    SC_CTOR(Range)
    {
      SC_METHOD(range_proc);
      sensitive << in;
    }
  };
  
  void Range::range_proc(void)
  {
    //out.write(in.read().range(0, 3));
    out.write(in.read().range(3, 0));
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in;
    sc_signal<sc_uint<8> > out;
  
    Range x("Range");
    x(in, out);
  
    sc_initialize();
  
    in = 0x55; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  85 5

「out.write(in.read().range(3, 0));」が
「out.write(in.read().range(0, 3));」だと以下のエラー
  Error: (E5) out of bounds: sc_uint[_base] part selection: left = 0, right = 3 violates 0 <= right <= left <= 7
  In file: ../../../../../src/systemc/datatypes/int/sc_uint_base.cpp:182
  In process: Range.range_proc @ 0 s
  0 0

!2007-02-05 Mon

bool でビット選択

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(extract)
  {
    sc_in <bool> in;
    sc_in <sc_uint<8> > n;
    sc_out<bool> out;
  
    void extract_proc(void);
  
    SC_CTOR(extract)
    {
      SC_METHOD(extract_proc);
      sensitive << in << n;
    }
  };
  
  void extract::extract_proc(void)
  {
    out.write(in.read()[n.read()]);
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<sc_uint<8> > n;
    sc_signal<bool> out;
  
    extract x("extract");
    x(in, n, out);
  
    sc_initialize();
  
    in = 0x55; n = 0; sc_start(1, SC_NS);
    cout << in << " " << n << " " << out << endl;
  
    return 0;
  }
で、
  2007020500.cpp: In method `void extract::extract_proc()':
  2007020500.cpp:24: no match for `const bool &[const sc_dt::sc_uint<8> &]'

!2007-02-04 Sun

連接

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Concat)
  {
    sc_in <sc_uint<4> > in1, in2;
    sc_out<sc_uint<8> > out;
  
    void concat_proc(void);
  
    SC_CTOR(Concat)
    {
      SC_METHOD(concat_proc);
      sensitive << in1 << in2;
    }
  };
  
  void Concat::concat_proc(void)
  {
    out.write((in1.read(), in2.read()));
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<4> > in1, in2;
    sc_signal<sc_uint<8> > out;
  
    Concat x("Concat");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 0xf; in2 = 0xf; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  1 1 17
  15 15 255

「out.write((in1.read(), in2.read()));」が
「out.write(in1.read(), in2.read());」だとダメらしい

!2007-02-03 Sat

シフト。シフト量が負だと？

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Shift)
  {
    sc_in <sc_uint<8> > in1, in2;
    sc_out<sc_int<8>  > out;
  
    void shift_proc(void);
  
    SC_CTOR(Shift)
    {
      SC_METHOD(shift_proc);
      sensitive << in1 << in2;
    }
  };
  
  void Shift::shift_proc(void)
  {
    out.write(in1.read() << in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in1, in2;
    sc_signal<sc_int<8>  > out;
  
    Shift x("Shift");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 1; in2 = -1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 1; in2 = -127; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  1 255 0
  1 129 2

ふむ

!2007-02-02 Fri

2007-02-01 のコードで「in = 0x55; n = 0; sc_start(1, SC_NS);」を
「in = 0x55; n = 8; sc_start(1, SC_NS);」に

  Error: (E5) out of bounds: sc_uint[_base] bit selection: index = 8 violates 0 <= index <= 7
  In file: ../../../../../src/systemc/datatypes/int/sc_uint_base.cpp:171
  In process: extract.extract_proc @ 0 s
  85 8 0

!2007-02-01 Thu

ビット選択

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(extract)
  {
    sc_in <sc_uint<8> > in;
    sc_in <sc_uint<8> > n;
    sc_out<bool> out;
  
    void extract_proc(void);
  
    SC_CTOR(extract)
    {
      SC_METHOD(extract_proc);
      sensitive << in << n;
    }
  };
  
  void extract::extract_proc(void)
  {
    out.write(in.read()[n.read()]);
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in;
    sc_signal<sc_uint<8> > n;
    sc_signal<bool> out;
  
    extract x("extract");
    x(in, n, out);
  
    sc_initialize();
  
    in = 0x55; n = 0; sc_start(1, SC_NS);
    cout << in << " " << n << " " << out << endl;
  
    in = 0x55; n = 1; sc_start(1, SC_NS);
    cout << in << " " << n << " " << out << endl;
  
    in = 0x55; n = 2; sc_start(1, SC_NS);
    cout << in << " " << n << " " << out << endl;
  
    return 0;
  }
で、
  85 0 1
  85 1 0
  85 2 1

ビット代入というものはある？？？

!2007-01-31 Wed

sc_lv

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(AND)
  {
    sc_in <sc_lv<8> > in1, in2;
    sc_out<sc_lv<8> > out;
  
    void and(void);
  
    SC_CTOR(AND)
    {
      SC_METHOD(and);
      sensitive << in1 << in2;
    }
  };
  
  void AND::and(void)
  {
    out.write(in1.read() & in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_lv<8> > in1, in2;
    sc_signal<sc_lv<8> > out;
  
    AND x("and");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 0; in2 = 0; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  00000000 00000000 00000000

SC_LOGIC_Z, SC_LOGIC_X 相当のものがあるのかは不明

!2007-01-30 Tue

sc_logic。不定の伝播

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(AND)
  {
    sc_in <sc_logic> in1, in2;
    sc_out<sc_logic> out;
  
    void and(void);
  
    SC_CTOR(AND)
    {
      SC_METHOD(and);
      sensitive << in1 << in2;
    }
  };
  
  void AND::and(void)
  {
    out.write(in1.read() & in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_logic> in1, in2;
    sc_signal<sc_logic> out;
  
    AND x("and");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = SC_LOGIC_0; in2 = SC_LOGIC_0; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in2 = SC_LOGIC_Z;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in2 = SC_LOGIC_X;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = SC_LOGIC_1; in2 = SC_LOGIC_1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in2 = SC_LOGIC_Z;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in2 = SC_LOGIC_X;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  0 0 0
  0 Z 0
  0 X 0
  1 1 1
  1 Z X
  1 X X

!2007-01-29 Mon

sc_logic

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <sc_logic>  in;
    sc_out<sc_logic> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_logic> in;
    sc_signal<sc_logic> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = SC_LOGIC_0;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = SC_LOGIC_1;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = SC_LOGIC_Z;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = SC_LOGIC_X;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  0 0
  1 1
  Z Z
  X X

!2007-01-28 Sun

sc_biguint

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Adder)
  {
    sc_in <sc_biguint<65> > in1, in2;
    sc_out<sc_biguint<65> > out;
  
    void add(void);
  
    SC_CTOR(Adder)
    {
      SC_METHOD(add);
      sensitive << in1 << in2;
    }
  };
  
  void Adder::add(void)
  {
    out.write(in1.read() + in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_biguint<65> > in1, in2;
    sc_signal<sc_biguint<65> > out;
  
    Adder x("Adder");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  1 1 2

!2007-01-27 Sat

2007-01-26 のコードで「sc_uint<64>」を「sc_uint<65>」に

コンパイルはできたが、実行で以下のエラー
  Error: (E5) out of bounds: sc_uint[_base] initialization: length = 65 violates 1 <= length <= 64
  In file: ../../../../../src/systemc/datatypes/int/sc_uint_base.cpp:160

!2007-01-26 Fri

2007-01-25 のコードで以下を変更
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
で、
  1 1 2

!2007-01-25 Thu

32ビットを超える数値(リテラル)

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Adder)
  {
    sc_in <sc_uint<64> > in1, in2;
    sc_out<sc_uint<64> > out;
  
    void add(void);
  
    SC_CTOR(Adder)
    {
      SC_METHOD(add);
      sensitive << in1 << in2;
    }
  };
  
  void Adder::add(void)
  {
    out.write(in1.read() + in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<64> > in1, in2;
    sc_signal<sc_uint<64> > out;
  
    Adder x("Adder");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 4294967296; in2 = 4294967296; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 281474976710656; in2 = 281474976710656; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  2007012500.cpp:36: integer constant out of range
  2007012500.cpp:36: warning: decimal integer constant is so large that it is unsigned

* どうやって入力すれば？
* そもそもリテラル自身何ビットまで認められているのだろうか？

!2007-01-24 Wed

2007-01-23 のコードで、sc_uint を sc_int に変更で、
  0 1 0
  0 0 0
  1 0 1
  -1 0 0

!2007-01-23 Tue

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(CMP)
  {
    sc_in <sc_uint<8> > in1, in2;
    sc_out<bool> out;
  
    void gt(void);
  
    SC_CTOR(CMP)
    {
      SC_METHOD(gt);
      sensitive << in1 << in2;
    }
  };
  
  void CMP::gt(void)
  {
    out.write(in1.read() > in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in1, in2;
    sc_signal<bool> out;
  
    CMP x("CMP");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 0; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 0; in2 = 0; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 1; in2 = 0; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 255; in2 = 0; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  0 1 0
  0 0 0
  1 0 1
  255 0 1

!2007-01-22 Mon

1ビットでも sc_int を使えるか？

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Adder)
  {
    sc_in <sc_int<1> > in1, in2;
    sc_out<sc_int<2> > out;
  
    void add(void);
  
    SC_CTOR(Adder)
    {
      SC_METHOD(add);
      sensitive << in1 << in2;
    }
  };
  
  void Adder::add(void)
  {
    out.write(in1.read() + in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_int<1> > in1, in2;
    sc_signal<sc_int<2> > out;
  
    Adder x("Adder");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 0; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  0 -1 -1
  -1 -1 -2

!2007-01-21 Sun

2007-01-20 のコードで sc_uint<1> を bool に変更で、
  0 1 1
  1 1 2

!2007-01-20 Sat

1ビットでも sc_uint を使えるか？

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Adder)
  {
    sc_in <sc_uint<1> > in1, in2;
    sc_out<sc_uint<2> > out;
  
    void add(void);
  
    SC_CTOR(Adder)
    {
      SC_METHOD(add);
      sensitive << in1 << in2;
    }
  };
  
  void Adder::add(void)
  {
    out.write(in1.read() + in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<1> > in1, in2;
    sc_signal<sc_uint<2> > out;
  
    Adder x("Adder");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 0; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  0 1 1
  1 1 2

!2007-01-19 Fri

2007-01-18 のコードで、以下を変更
    in1 = -1; in2 = -1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
で、
  255 255 510

!2007-01-18 Thu

sc_uint + adder

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(Adder)
  {
    sc_in <sc_uint<8> > in1, in2;
    sc_out<sc_uint<9> > out;
  
    void add(void);
  
    SC_CTOR(Adder)
    {
      SC_METHOD(add);
      sensitive << in1 << in2;
    }
  };
  
  void Adder::add(void)
  {
    out.write(in1.read() + in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in1, in2;
    sc_signal<sc_uint<9> > out;
  
    Adder x("Adder");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = 1; in2 = 1; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = 255; in2 = 255; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  1 1 2
  255 255 510

!2007-01-17 Wed

2007-01-16 のコードで、以下を変更
    in = 511;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = 0;    sc_start(1, SC_NS);
    cout << in << " " << out << endl;
で、
  255 255
  0 0

あふれ分のチェックはないのか。まあそんなものかも。

!2007-01-16 Tue

sc_uint

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <sc_uint<8> >  in;
    sc_out<sc_uint<8> > out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<sc_uint<8> > in;
    sc_signal<sc_uint<8> > out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1
  0 0

bool との型チェックのようなものは行なわれないようだ。
そもそも C++ でチェックがないからか？

!2007-01-15 Mon

vcd 出力

2007-01-14 のコードで、
  ((vcd_trace_file *)trace_f) -> sc_set_vcd_time_unit(-9);
を
  ((vcd_trace_file *)trace_f) -> sc_set_vcd_time_unit(-6);
にすると、
  Note: VCD trace timescale unit is set by user to 1e-6 sec.
  1 1
  0 0
しかし、「sc_start(1, SC_NS);」のままだったので、
gtkwave で表示できず怒られてしまった…
  VCD times range is equal to zero.  Exiting.

上記変更に加え、
  sc_start(1, SC_US);
に変更で OK

!2007-01-14 Sun

vcd 出力

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_trace_file *trace_f;
    trace_f = sc_create_vcd_trace_file("2007011400");
    ((vcd_trace_file *)trace_f) -> sc_set_vcd_time_unit(-9);
  
    sc_trace(trace_f, in, "In");
    sc_trace(trace_f, out, "Out");
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    sc_close_vcd_trace_file(trace_f);
  
    return 0;
  }
で、
  Note: VCD trace timescale unit is set by user to 1e-9 sec.
  1 1
  0 0

!2007-01-13 Sat

ポインタ変数を使ってインスタンス化

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
    buffer *b1;
  
    b1 = new buffer("buffer");
    (*b1)(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1
  0 0

!2007-01-12 Fri

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(AND)
  {
    sc_in <bool> in1, in2;
    sc_out<bool> out;
  
    void and(void);
  
    SC_CTOR(AND)
    {
      SC_METHOD(and);
      sensitive << in1 << in2;
    }
  };
  
  void AND::and(void)
  {
    out.write(in1.read() & in2.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in1, in2;
    sc_signal<bool> out;
  
    AND x("and");
    x(in1, in2, out);
  
    sc_initialize();
  
    in1 = false; in2 = false; sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = false; in2 = true;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    in1 = true;  in2 = true;  sc_start(1, SC_NS);
    cout << in1 << " " << in2 << " " << out << endl;
  
    return 0;
  }
で、
  0 0 0
  0 1 0
  1 1 1

* モジュール名とプロセス名が同じだとダメらしい…
* 「sensitive << in1 << in2;」を「sensitive << in1;」にしても動作しちゃうな

!2007-01-11 Thu

ピンの名前。登録方法

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool> buf_in;
    sc_out<bool> buf_out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << buf_in;
    }
  };
  
  void buffer::buf(void)
  {
    buf_out.write(buf_in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> m_in;
    sc_signal<bool> m_out;
  
    buffer b1("buffer");
    b1.buf_in (m_in);
    b1.buf_out(m_out);
  
    sc_initialize();
  
    m_in = true;  sc_start(1, SC_NS);
    cout << m_in << " " << m_out << endl;
  
    m_in = false; sc_start(1, SC_NS);
    cout << m_in << " " << m_out << endl;
  
    return 0;
  }
で、
  1 1
  0 0

「b1.buf_out(m_out);」をコメントアウトして登録し忘れると、
実行時に以下のエラー
  Error: (E109) complete binding failed: port not bound: port 'buffer.port_1' (sc_out)
  In file: ../../../../src/systemc/communication/sc_port.cpp:196

!2007-01-10 Wed

2007-01-06 のコードで、「sc_start(1, SC_NS);」を「sc_start(0.1, SC_NS);」に

  1 1
  0 0

昨日のメッセージからするとダメかと思ったのに、いちおう実行できた。

!2007-01-09 Tue

2007-01-06 のコードで、「sc_start(1, SC_NS);」を「sc_start(0, SC_NS);」に

  1 1
  run.x: ../../../../src/systemc/utils/sc_pq.cpp:63: void * sc_ppq_base::extract_top(): Assertion `m_heap_size > 0' failed.
  アボートしました

!2007-01-08 Mon

2007-01-06 のコードで、「sc_start(1, SC_NS);」をコメントアウト

  0 0
  0 0

!2007-01-07 Sun

2007-01-06 のコードで、「sc_initialize();」をコメントアウト

動いてしまう…。trace とか使わないと大丈夫なのか？？？

!2007-01-06 Sat

  #include <iostream>
  #include "systemc.h"
  
  SC_MODULE(buffer)
  {
    sc_in <bool>  in;
    sc_out<bool> out;
  
    void buf(void);
  
    SC_CTOR(buffer)
    {
      SC_METHOD(buf);
      sensitive << in;
    }
  };
  
  void buffer::buf(void)
  {
    out.write(in.read());
  }
  
  int sc_main(int argc, char *argv[])
  {
    sc_signal<bool> in;
    sc_signal<bool> out;
  
    buffer b1("buffer");
    b1(in, out);
  
    sc_initialize();
  
    in = true;  sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    in = false; sc_start(1, SC_NS);
    cout << in << " " << out << endl;
  
    return 0;
  }
で、
  1 1
  0 0

* ひとつのファイルで書いても動くことは動くようだ
* SC_METHOD と他なのとの違いは？(←今後 確認)

!2007-01-05 Fri

  #include <iostream>
  #include "systemc.h"
  
  int sc_main(int argc, char *argv[])
  {
  
    return 0;
  }
で、
  $ ./run.x 
  
               SystemC 2.0.1 --- Feb  5 2004 16:36:48
          Copyright (c) 1996-2002 by all Contributors
                      ALL RIGHTS RESERVED

「#include "systemc.h"」と「#include <systemc.h>」どっちが良いのだろう？

!2007-01-04 Thu

そういえば、2007-01-01 では entity の中に宣言を書かなかったぞ？
書いたらどうなる？

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
    procedure foo(x : in std_logic; out_x : out std_logic);
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2007010400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2007010400.out";  -- VHDL '93
  
    procedure foo(x : in std_logic; out_x : out std_logic) is
      begin
        out_x := not x;
      end foo;
  
  begin
    process
      variable lo : line;
      variable OUT_X: std_logic;
    begin
      foo('1', OUT_X); wait for 1 ns; write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
      foo('0', OUT_X); wait for 1 ns; write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

!2007-01-03 Wed

package の中で名前が衝突したら？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    type BYTE is array (7 downto 0) of std_logic;
  end FOO;
  
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package BAR is
    type BYTE is array (7 downto 0) of std_logic;
  end BAR;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  use WORK.BAR.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_X: WORK.FOO.BYTE;
    -- file outv : text is out "2007010300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2007010300.out";  -- VHDL '93
  
  begin
    process
    begin
      IN_X <= "00000000"; wait for 1 ns;
      IN_X <= "11111111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); -- write(lo, IN_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

「WORK.FOO.BYTE」を「BYTE」としたらエラーに

!2007-01-02 Tue

type もローカルで使うだけなら package は不要だった。
ローカルで使うという場面は特殊かもしれないが？

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2007010200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2007010200.out";  -- VHDL '93
  
    type OPE is (OPE_THROUGH, OPE_NOT);
  
    procedure foo(x : in std_logic; t : in OPE; out_x : out std_logic) is
    begin
      if (t = OPE_NOT) then
        out_x := not x;
      else
        out_x := x;
      end if;
    end foo;
  
  begin
    process
      variable lo : line;
      variable OUT_X: std_logic;
    begin
      foo('1', OPE_NOT,     OUT_X); wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
  
      foo('0', OPE_NOT,     OUT_X); wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
  
      foo('1', OPE_THROUGH, OUT_X); wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
  
      foo('0', OPE_THROUGH, OUT_X); wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 1
  3 ns 1
  4 ns 0

!2007-01-01 Mon

procedure これも package がなくても良かったようだ…

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2007010100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2007010100.out";  -- VHDL '93
  
    procedure foo(x : in std_logic; out_x : out std_logic) is
      begin
        out_x := not x;
      end foo;
  
  begin
    process
      variable lo : line;
      variable OUT_X: std_logic;
    begin
      foo('1', OUT_X); wait for 1 ns; write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
      foo('0', OUT_X); wait for 1 ns; write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 1
  3 ns 0

!2006-12-31 Sun

function

package を使わないとダメなのかと勘違いしていたが、違ったようだ…

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006123100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006123100.out";  -- VHDL '93
    signal OUT_X: std_logic;
  
    function foo (x : std_logic) return std_logic is
    begin
      return '0';
    end foo;
  
  begin
    process
    begin
      OUT_X <= foo('1');
      wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 0
  3 ns 0

!2006-12-30 Sat

function の引数にわざわざ in をつけてみる

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    function foo (x : in std_logic) return std_logic;
  end FOO;
  
  package body FOO is
    function foo (x : in std_logic) return std_logic is
      begin
        return '0';
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006123000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006123000.out";  -- VHDL '93
    signal OUT_X: std_logic;
  
  begin
    process
    begin
      OUT_X <= foo('1');
      wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 0
  3 ns 0

宣言(?)と body で in の有無を変えても大丈夫なようだ

!2006-12-29 Fri

タイプ変換、To_bit

0,1 以外を指定したら？

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_X  : std_logic;
    signal OUT_X : bit;
    -- file outv : text is out "2006122900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122900.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      IN_X <= '0'; OUT_X <= To_bit(IN_X); wait for 1 ns;
      IN_X <= '1'; OUT_X <= To_bit(IN_X); wait for 1 ns;
      IN_X <= 'U'; OUT_X <= To_bit(IN_X); wait for 1 ns;
      IN_X <= 'X'; OUT_X <= To_bit(IN_X); wait for 1 ns;
      IN_X <= 'Z'; OUT_X <= To_bit(IN_X); wait for 1 ns;
      IN_X <= '-'; OUT_X <= To_bit(IN_X); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 2); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0
  2 ns 1 0
  3 ns U 1
  4 ns X 0
  5 ns Z 0
  6 ns - 0
  7 ns 0 0

!2006-12-28 Thu

タイプ変換、To_bit

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_X  : std_logic;
    signal OUT_X : bit;
    -- file outv : text is out "2006122800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122800.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      IN_X <= '0'; OUT_X <= To_bit(IN_X); wait for 1 ns;
      IN_X <= '1'; OUT_X <= To_bit(IN_X); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 2); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0
  2 ns 1 0
  3 ns 0 1

!2006-12-27 Wed

タイプ変換、To_stdlogic

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_X  : bit;
    signal OUT_X : std_logic;
    -- file outv : text is out "2006122700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122700.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      IN_X <= '0'; OUT_X <= To_stdlogic(IN_X); wait for 1 ns;
      IN_X <= '1'; OUT_X <= To_stdlogic(IN_X); wait for 1 ns;
      -- ** Error: 2006122700.vhdl(24): Unknown identifier 'to_stdlogic'.
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 2); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

そんなものないと怒られた〜

!2006-12-26 Tue

タイプ変換、To_bitvector

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_X  : std_logic_vector(3 downto 0);
    signal OUT_X : bit_vector(3 downto 0);
    -- file outv : text is out "2006122600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122600.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      IN_X <= "0000"; OUT_X <= To_bitvector(IN_X); wait for 1 ns;
      IN_X <= "1111"; OUT_X <= To_bitvector(IN_X); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 0000
  2 ns 1111 0000
  3 ns 0000 1111

!2006-12-25 Mon

タイプ変換、To_stdlogicvector

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_X  : bit_vector(3 downto 0);
    signal OUT_X : std_logic_vector(3 downto 0);
    -- file outv : text is out "2006122500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122500.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      IN_X <= "0000"; OUT_X <= To_stdlogicvector(IN_X); wait for 1 ns;
      IN_X <= "1111"; OUT_X <= To_stdlogicvector(IN_X); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 0000
  2 ns 1111 0000
  3 ns 0000 1111

!2006-12-24 Sun

配列タイプ 可変長

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    type MEMORY is array (integer range <>) of std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_unsigned.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    constant ROM : MEMORY(0 to 3) := ("00000000", "00000001", "00000010", "00000011");
    signal IN_X  : std_logic_vector(3 downto 0);
    signal OUT_X : std_logic_vector(7 downto 0);
    -- file outv : text is out "2006122400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122400.out";  -- VHDL '93
  
  begin
    process
    begin
      IN_X <= "0000"; wait for 1 ns;
      IN_X <= "0001"; wait for 1 ns;
      IN_X <= "0010"; wait for 1 ns;
      IN_X <= "0011"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, ROM(conv_integer(IN_X)), right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 00000000
  2 ns 0001 00000001
  3 ns 0010 00000010
  4 ns 0011 00000011

初期値の数からサイズを推定してくれるという素晴らしい機能はないようだ

!2006-12-23 Sat

2次元配列

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    type MEMORY is array (0 to 3, 0 to 3) of std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_unsigned.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    constant ROM : MEMORY := (("00000000", "00000001", "00000010", "00000011"),
                              ("00010000", "00010001", "00010010", "00010011"),
                              ("00100000", "00100001", "00100010", "00100011"),
                              ("00110000", "00110001", "00110010", "00110011"));
    signal IN_X, IN_Y : std_logic_vector(1 downto 0);
    signal OUT_X : std_logic_vector(7 downto 0);
    -- file outv : text is out "2006122300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122300.out";  -- VHDL '93
  
  begin
    process
    begin
      IN_Y <= "00"; wait for 1 ns;
      IN_X <= "00"; wait for 1 ns;
      IN_X <= "01"; wait for 1 ns;
      IN_X <= "10"; wait for 1 ns;
      IN_X <= "11"; wait for 1 ns;
  
      IN_Y <= "01"; wait for 1 ns;
      IN_Y <= "10"; wait for 1 ns;
      IN_Y <= "11"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, ROM(conv_integer(IN_X), conv_integer(IN_Y)), right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns   UU 00000000
  2 ns   00 00000000
  3 ns   01 00010000
  4 ns   10 00100000
  5 ns   11 00110000
  6 ns   11 00110001
  7 ns   11 00110010
  8 ns   11 00110011

論理合成はできないらしいよ

!2006-12-22 Fri

配列 again

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    type MEMORY is array (0 to 3) of std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_unsigned.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal ROM   : MEMORY;
    signal IN_X  : std_logic_vector(3 downto 0);
    signal OUT_X : std_logic_vector(7 downto 0);
    -- file outv : text is out "2006122200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122200.out";  -- VHDL '93
  
  begin
    process
    begin
      ROM(0) <= "00000000"; wait for 1 ns;
      ROM(1) <= "00000001"; wait for 1 ns;
      ROM(2) <= "00000010"; wait for 1 ns;
  
      IN_X <= "0000"; wait for 1 ns;
      IN_X <= "0001"; wait for 1 ns;
      IN_X <= "0010"; wait for 1 ns;
      IN_X <= "0011"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, ROM(conv_integer(IN_X)), right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns UUUU 00000000
  2 ns UUUU 00000000
  3 ns UUUU 00000000
  4 ns 0000 00000000
  5 ns 0001 00000001
  6 ns 0010 00000010
  7 ns 0011 UUUUUUUU

!2006-12-21 Thu

配列 again

昨日ので、downto -> to に

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    type MEMORY is array (0 to 3) of std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_unsigned.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    constant ROM : MEMORY := ("00000000", "00000001", "00000010", "00000011");
    signal IN_X  : std_logic_vector(3 downto 0);
    signal OUT_X : std_logic_vector(7 downto 0);
    -- file outv : text is out "2006122100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122100.out";  -- VHDL '93
  
  begin
    process
    begin
      IN_X <= "0000"; wait for 1 ns;
      IN_X <= "0001"; wait for 1 ns;
      IN_X <= "0010"; wait for 1 ns;
      IN_X <= "0011"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, ROM(conv_integer(IN_X)), right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 00000000
  2 ns 0001 00000001
  3 ns 0010 00000010
  4 ns 0011 00000011

!2006-12-20 Wed

配列 again

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    type MEMORY is array (3 downto 0) of std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_unsigned.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    constant ROM : MEMORY := ("00000000", "00000001", "00000010", "00000011");
    signal IN_X  : std_logic_vector(3 downto 0);
    signal OUT_X : std_logic_vector(7 downto 0);
    -- file outv : text is out "2006122000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006122000.out";  -- VHDL '93
  
  begin
    process
    begin
      IN_X <= "0000"; wait for 1 ns;
      IN_X <= "0001"; wait for 1 ns;
      IN_X <= "0010"; wait for 1 ns;
      IN_X <= "0011"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, ROM(conv_integer(IN_X)), right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 00000011
  2 ns 0001 00000010
  3 ns 0010 00000001
  4 ns 0011 00000000

* 思っていたのとはアドレス方向が逆
* 「array (3 downto 0)」だと配列初期値に4つ、「array (7 downto 0)」だと配列初期値に8つ入れておかないとダメ
* conv_integer() がないとエラーに

!2006-12-19 Tue

数字に「_」入りまくりでも OK。
おまけに 0 を前置

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006121900.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006121900.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable i  : INTEGER;
      begin
        wait for 1 ns;
        write(lo, 1, right, 4); i := 0_0_2_5_6;
        write(lo, i, right, 4);
        writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
     1 256
     1 256

!2006-12-18 Mon

Z は z だとダメ？

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006121800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121800.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
      variable b  : std_logic;
    begin
      wait for 1 ns;
  
      b := 'z';  write(lo, b, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルエラー

!2006-12-17 Sun

X は x だとダメ

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006121700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121700.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
      variable b  : std_logic;
    begin
      wait for 1 ns;
  
      b := 'x';  write(lo, b, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルエラー

!2006-12-16 Sat

case 文。信号が部分信号でも大丈夫？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  std_logic_vector(3 downto 0);
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C(2 downto 0) is
        when "001"  => OUT_SEL2 <= A;
        when "010"  => OUT_SEL2 <= B;
        when others => OUT_SEL2 <= A and B;
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  std_logic_vector(3 downto 0);
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       std_logic_vector(3 downto 0);
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006121600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121600.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <= "1001"; wait for 1 ns;
                                IN_C <= "1010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
                   IN_B <= '1'; IN_C <= "1001"; wait for 1 ns;
                                IN_C <= "1010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 5);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0 1001 1
  2 ns 1 0 1010 0
  3 ns 1 0 1111 0
  4 ns 1 1 1001 1
  5 ns 1 1 1010 1
  6 ns 1 1 1111 1

!2006-12-15 Fri

case 文。範囲指定に重なりがあったら？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  integer range 0 to 15;
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C is
        when 0 to 3 => OUT_SEL2 <= A;
        when 2 to 5 => OUT_SEL2 <= B;
        when others => OUT_SEL2 <= A and B;
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  integer range 0 to 15;
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       integer range 0 to 15;
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006121500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121500.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <=  1; wait for 1 ns;
                                IN_C <=  3; wait for 1 ns;
                                IN_C <=  5; wait for 1 ns;
                                IN_C <= 15; wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; IN_C <=  1; wait for 1 ns;
                                IN_C <=  3; wait for 1 ns;
                                IN_C <=  5; wait for 1 ns;
                                IN_C <= 15; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 3);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイル エラー。さすがにチェックしていた

!2006-12-14 Thu

don't care 再び

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  std_logic_vector(3 downto 0);
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      if (C = "0001") then
        OUT_SEL2 <= A;
      elsif (C(3) = '0' and C(2) = '0' and C(1) = '1' and C(0) = '-') then
        OUT_SEL2 <= B;
      else
        OUT_SEL2 <= A and B;
      end if;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  std_logic_vector(3 downto 0);
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       std_logic_vector(3 downto 0);
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006121400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121400.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
                   IN_B <= '1'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 5);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0 0001 1
  2 ns 1 0 0010 0
  3 ns 1 0 1111 0
  4 ns 1 1 0001 1
  5 ns 1 1 0010 1
  6 ns 1 1 1111 1

そもそも don't care で書く必要が全くないけど…
(std_logic_vector のリテラルで don't care が書けなかったから…)

!2006-12-13 Wed

don't care

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  std_logic;
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C is
        when '0'    => OUT_SEL2 <= A;
        when '1'    => OUT_SEL2 <= '-';
        when others => OUT_SEL2 <= B;
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  std_logic;
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       std_logic;
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006121300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121300.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
                   IN_B <= '1'; IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 5);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0    0 1
  2 ns 1 0    1 -
  3 ns 1 1    0 1
  4 ns 1 1    1 -

don't care を出力ってどういう意味なんだろう？

!2006-12-12 Tue

ハイインピーダンス

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  std_logic;
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C is
        when '0'    => OUT_SEL2 <= A;
        when '1'    => OUT_SEL2 <= B;
        when others => OUT_SEL2 <= 'Z';
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  std_logic;
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       std_logic;
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006121200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121200.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
                   IN_B <= '1'; IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 5);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

普通の信号にハイインピーダンスを入れても良いみたい

!2006-12-11 Mon

abs があるらしいのだが？

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  -- use IEEE.std_logic_unsigned.ALL;
  
  entity OPE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_X <= abs(A);
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006121100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006121100.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルできなかった…

!2006-12-10 Sun

固定値を直接？
今度は、std_logic_vector で

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic_vector(7 downto 0);
            OUT_AND2: out std_logic_vector(7 downto 0));
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic_vector(7 downto 0);
                OUT_AND2: out std_logic_vector(7 downto 0));
      end component;
  
      signal IN_A:     std_logic_vector(7 downto 0);
      signal OUT_AND2: std_logic_vector(7 downto 0);
      -- file outv : text is out "2006121000.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006121000.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => "11111111",
        OUT_AND2 => OUT_AND2
      );
  
      process
      begin
        IN_A <= "00000000"; wait for 1 ns;
        IN_A <= "11111111"; wait for 1 ns;
      end process;
  
      process
      variable lo : line;
      begin
        wait for 1 ns;
        write(lo, NOW, right, 4); write(lo, IN_A, right, 9);
        write(lo, OUT_AND2, right, 9); writeline(outv, lo);
      end process;
  
  end TESTBENCH;

うむ、また動いてしまった。
直接書けないから信号に代入して使えみたいなことが書いてあったのに…。

!2006-12-09 Sat

固定値を直接？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:         in  std_logic;
          OUT_1, OUT_2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_1 <= A and B;
    OUT_2 <= not (A and B);
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:          in std_logic;
            OUT_1, OUT_2: out std_logic);
    end component;
  
    signal IN_A:     std_logic;
    signal OUT_AND2: std_logic;
    -- file outv : text is out "2006120900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006120900.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => '1',
      OUT_1 => OUT_AND2,
      OUT_2 => open
    );
  
    process
    begin
      IN_A <= '0'; wait for 1 ns;
      IN_A <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

正しく動くみたい

!2006-12-08 Fri

「open」(ファイルのじゃなくて)
今度は出力。

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:         in  std_logic;
          OUT_1, OUT_2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_1 <= A and B;
    OUT_2 <= not (A and B);
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:          in std_logic;
            OUT_1, OUT_2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006120800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006120800.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_1 => OUT_AND2,
      OUT_2 => open
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

動作した。

!2006-12-07 Thu

「open」(ファイルのじゃなくて)

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B, C:  in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B, C:   in std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006120700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006120700.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => open,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルエラーだった…。
入力には使えない？？？

!2006-12-06 Wed

未使用端子があったら？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B, C:  in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B, C:   in std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B, IN_C: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006120600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006120600.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

* 特に怒られなかった。
* port に矛盾があったりするとダメみたい。あたりまえだけど。

!2006-12-05 Tue

time 型。/ * は使えるようだ。+ - はダメだった。

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    constant STEP : time := 10 ns;
    -- file outv : text is out "2006120500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006120500.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for STEP / 2;
      IN_A <= '1';              wait for STEP * 2;
      IN_A <= '0'; IN_B <= '1'; wait for STEP; -- + 1;
      IN_A <= '1';              wait for STEP; -- - 1;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

!2006-12-04 Mon

time 型

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    constant STEP : time := 1 ns;
    -- file outv : text is out "2006120400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006120400.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for STEP;
      IN_A <= '1';              wait for STEP;
      IN_A <= '0'; IN_B <= '1'; wait for STEP;
      IN_A <= '1';              wait for STEP;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

!2006-12-03 Sun

others による初期化。+ による更新
IN_X から IN_A, IN_B に直接接続

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic_vector(1 downto 0);
            OUT_AND2: out std_logic_vector(1 downto 0));
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic_vector(1 downto 0);
                OUT_AND2: out std_logic_vector(1 downto 0));
      end component;
  
      signal IN_X:       std_logic_vector(3 downto 0);
      signal IN_A, IN_B: std_logic_vector(1 downto 0);
      signal OUT_AND2:   std_logic_vector(1 downto 0);
      -- file outv : text is out "2006120300.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006120300.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      IN_A <= IN_X(3 downto 2); IN_B <= IN_X(1 downto 0);
  
      process
      begin
        IN_X <= (others => '0');
  
        for i in 0 to 15 loop
          wait for 1 ns;
          IN_X <= IN_X + '1';
        end loop;
      end process;
  
      process
      variable lo : line;
      begin
        wait for 1 ns;
        write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, IN_A, right, 3); write(lo, IN_B, right, 3);
        write(lo, OUT_AND2, right, 5); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  1 ns 0000 00 00   00
  2 ns 0001 00 01   00
  3 ns 0010 00 10   00
  4 ns 0011 00 11   00
  5 ns 0100 01 00   00
  6 ns 0101 01 01   01
  7 ns 0110 01 10   00
  8 ns 0111 01 11   01
  9 ns 1000 10 00   00
  10 ns 1001 10 01   00
  11 ns 1010 10 10   10
  12 ns 1011 10 11   10
  13 ns 1100 11 00   00
  14 ns 1101 11 01   01
  15 ns 1110 11 10   10
  16 ns 1111 11 11   11

!2006-12-02 Sat

others による初期化。+ による更新

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic_vector(1 downto 0);
            OUT_AND2: out std_logic_vector(1 downto 0));
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic_vector(1 downto 0);
                OUT_AND2: out std_logic_vector(1 downto 0));
      end component;
  
      signal IN_X:       std_logic_vector(3 downto 0);
      signal IN_A, IN_B: std_logic_vector(1 downto 0);
      signal OUT_AND2:   std_logic_vector(1 downto 0);
      -- file outv : text is out "2006120200.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006120200.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      begin
        IN_X <= (others => '0');
  
        for i in 0 to 15 loop
          wait for 1 ns;
          IN_A <= IN_X(3 downto 2); IN_B <= IN_X(1 downto 0);
          IN_X <= IN_X + '1';
        end loop;
      end process;
  
      process
      variable lo : line;
      begin
        wait for 1 ns;
        write(lo, NOW, right, 4); write(lo, IN_X, right, 5); write(lo, IN_A, right, 3); write(lo, IN_B, right, 3);
        write(lo, OUT_AND2, right, 5); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  1 ns 0000 UU UU   UU
  2 ns 0001 00 00   00
  3 ns 0010 00 01   00
  4 ns 0011 00 10   00
  5 ns 0100 00 11   00
  6 ns 0101 01 00   00
  7 ns 0110 01 01   01
  8 ns 0111 01 10   00
  9 ns 1000 01 11   01
  10 ns 1001 10 00   00
  11 ns 1010 10 01   00
  12 ns 1011 10 10   10
  13 ns 1100 10 11   10
  14 ns 1101 11 00   00
  15 ns 1110 11 01   01
  16 ns 1111 11 10   10

assign みたいな記述ってどうやるんだっけ？

!2006-12-01 Fri

演算子優先度。混ぜるとダメ

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity OPE is
    port (A, B, C: in  std_logic;
          OUT_OPE: out std_logic);
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_OPE <= A and B or C;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A, B, C: in  std_logic;
            OUT_OPE: out std_logic);
    end component;
  
    signal IN_A, IN_B, IN_C: std_logic;
    signal OUT_OPE:          std_logic;
    -- file outv : text is out "2006120100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006120100.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_OPE => OUT_OPE
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; IN_C <= '0'; wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
      IN_A <= '0'; IN_B <= '1';              wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
      IN_A <= '0'; IN_B <= '0'; IN_C <= '1'; wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
      IN_A <= '0'; IN_B <= '1';              wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 2);
      write(lo, OUT_OPE, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルエラー

!2006-11-30 Thu

演算子優先度。not は高い

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity OPE is
    port (A, B:     in  std_logic;
          OUT_OPE: out std_logic);
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_OPE <= A and not B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A, B:     in  std_logic;
            OUT_OPE: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_OPE:   std_logic;
    -- file outv : text is out "2006113000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006113000.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A        => IN_A,
      B        => IN_B,
      OUT_OPE => OUT_OPE
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_OPE, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 1
  3 ns 0 1 0
  4 ns 1 1 0

!2006-11-29 Wed

xnor

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity XNOR2 is
    port (A, B:      in  std_logic;
          OUT_XNOR2: out std_logic);
  end XNOR2;
  
  architecture RTL of XNOR2 is
  begin
    OUT_XNOR2 <= A xnor B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component XNOR2
      port (A, B:      in  std_logic;
            OUT_XNOR2: out std_logic);
    end component;
  
    signal IN_A, IN_B:  std_logic;
    signal OUT_XNOR2:   std_logic;
    -- file outv : text is out "2006112900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112900.out";  -- VHDL '93
  
  begin
    DUT: XNOR2 port map (
      A         => IN_A,
      B         => IN_B,
      OUT_XNOR2 => OUT_XNOR2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_XNOR2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 1
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1

!2006-11-28 Tue

「;」の扱い

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006112800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112800.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
      variable b  : BOOLEAN;
    begin
      wait for 1 ns;
      write(lo, TRUE, right, 5); write(lo, FALSE, right, 6);
  
      ;

      b := TRUE;  write(lo, b, right, 5);
      b := FALSE; write(lo, b, right, 6);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルエラー

Pascal みたいなイメージなのだろうか？？？

!2006-11-27 Mon

buffer

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND3 is
    port (A, B, C:            in     std_logic;
          OUT_AND2, OUT_AND3: buffer std_logic);
  end AND3;
  
  architecture RTL of AND3 is
  begin
    OUT_AND2 <= A and B;
    OUT_AND3 <= OUT_AND2 and C;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND3
      port (A, B, C:            in     std_logic;
            OUT_AND2, OUT_AND3: buffer std_logic);
    end component;
  
    signal IN_A, IN_B, IN_C:     std_logic;
    signal OUT_AND2, OUT_AND3:   std_logic;
    -- file outv : text is out "2006112700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112700.out";  -- VHDL '93
  
  begin
    DUT: AND3 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_AND2 => OUT_AND2,
      OUT_AND3 => OUT_AND3
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; IN_C <= '0'; wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
      IN_A <= '0'; IN_B <= '1';              wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
      IN_A <= '0'; IN_B <= '0'; IN_C <= '1'; wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
      IN_A <= '0'; IN_B <= '1';              wait for 1 ns;
      IN_A <= '1';                           wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 2);
      write(lo, OUT_AND2, right, 2); write(lo, OUT_AND3, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0 0 0
  2 ns 1 0 0 0 0
  3 ns 0 1 0 0 0
  4 ns 1 1 0 1 0
  5 ns 0 0 1 0 0
  6 ns 1 0 1 0 0
  7 ns 0 1 1 0 0
  8 ns 1 1 1 1 1

!2006-11-26 Sun

buffer

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in     std_logic;
          OUT_AND2: buffer std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in     std_logic;
            OUT_AND2: buffer std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006112600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112600.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1

良く分からないけど大丈夫だった

!2006-11-25 Sat

識別子の最後に _ はダメ

なぜそのような仕様に？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT_AND2_: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2_ <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT_AND2_: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2_:   std_logic;
    -- file outv : text is out "2006112500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112500.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_AND2_ => OUT_AND2_
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2_, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルエラー

!2006-11-24 Fri

識別子に __ はダメ

なぜそのような仕様に？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT__AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT__AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT__AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT__AND2:   std_logic;
    -- file outv : text is out "2006112400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112400.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT__AND2 => OUT__AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT__AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

コンパイルエラー

!2006-11-23 Thu

configuration

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH1 of TESTBNCH is
    -- file outv : text is out "2006112300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112300.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, TRUE, right, 5); write(lo, FALSE, right, 6);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH1;
  
  architecture TESTBENCH2 of TESTBNCH is
    -- file outv : text is out "2006112300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112300.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, FALSE, right, 6); write(lo, TRUE, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH2;
  
  configuration CFG of TESTBNCH is
    for TESTBENCH1
    end for;
  end CFG;
で、
   FALSE TRUE

* うまく動いているようには思えない。どうやれば？
* CFG をトップモジュールにしたら TESTBENCH1 でも TESTBENCH2 でも「 TRUE FALSE」。謎
* 「architecture TESTBENCH of TESTBNCH is」の「TESTBNCH」はどこから持ってきたものだろう？

!2006-11-22 Wed

unsigned(), signed()

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  -- use IEEE.std_logic_unsigned.ALL;
  
  entity OPE is
    port (A, B:           in  std_logic_vector(3 downto 0);
          OUT_X1, OUT_X2: out std_logic_vector(3 downto 0));
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_X1 <=   signed(A) +   signed(B);
    OUT_X2 <= unsigned(A) + unsigned(B);
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A, B:           in  std_logic_vector(3 downto 0);
            OUT_X1, OUT_X2: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A, IN_B:     std_logic_vector(3 downto 0);
    signal OUT_X1, OUT_X2: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006112200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112200.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A      => IN_A,
      B      => IN_B,
      OUT_X1 => OUT_X1,
      OUT_X2 => OUT_X2
    );
  
    process
    begin
      IN_A <= "0001"; IN_B <= "0001"; wait for 1 ns;
      IN_A <= "1000"; IN_B <= "0001"; wait for 1 ns;
      IN_A <= "1111"; IN_B <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      write(lo, OUT_X1, right, 5); write(lo, OUT_X2, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0001 0001 0010 0010
  2 ns 1000 0001 1001 1001
  3 ns 1111 1111 1110 1110

unsigned() を使う場面が良く分からない

!2006-11-21 Tue

比較 signed で

  library IEEE;
  use IEEE.std_logic_1164.all;
  -- use IEEE.std_logic_unsigned.all;
  use IEEE.std_logic_arith.all;
  
  entity CMP is
    port (A, B: in std_logic_vector(3 downto 0);
          OUT_X1, OUT_X2, OUT_X3, OUT_X4: out std_logic);
  end CMP;
  
  architecture RTL of CMP is
  begin
    OUT_X1 <= '1' when signed(A) >  signed(B) else '0';
    OUT_X2 <= '1' when signed(A) >= signed(B) else '0';
    OUT_X3 <= '1' when signed(A) <  signed(B) else '0';
    OUT_X4 <= '1' when signed(A) <= signed(B) else '0';
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component CMP
      port (A, B: in std_logic_vector(3 downto 0);
            OUT_X1, OUT_X2, OUT_X3, OUT_X4: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic_vector(3 downto 0);
    signal OUT_X1, OUT_X2, OUT_X3, OUT_X4: std_logic;
    -- file outv : text is out "2006112100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112100.out";  -- VHDL '93
  
  begin
    DUT: CMP port map (
      A      => IN_A,
      B      => IN_B,
      OUT_X1 => OUT_X1,
      OUT_X2 => OUT_X2,
      OUT_X3 => OUT_X3,
      OUT_X4 => OUT_X4
    );
  
    process
    begin
      IN_A <= "0000"; IN_B <= "0000"; wait for 1 ns;
      IN_A <= "1111";                 wait for 1 ns;
      IN_A <= "0000"; IN_B <= "1111"; wait for 1 ns;
      IN_A <= "1111";                 wait for 1 ns;
  
      IN_A <= "0111"; IN_B <= "0000"; wait for 1 ns;
      IN_A <= "0000"; IN_B <= "0111"; wait for 1 ns;
      IN_A <= "0111";                 wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      write(lo, OUT_X1, right, 2); write(lo, OUT_X2, right, 2);
      write(lo, OUT_X3, right, 2); write(lo, OUT_X4, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 0000 0 1 0 1
  2 ns 1111 0000 0 0 1 1
  3 ns 0000 1111 1 1 0 0
  4 ns 1111 1111 0 1 0 1
  5 ns 0111 0000 1 1 0 0
  6 ns 0000 0111 0 0 1 1
  7 ns 0111 0111 0 1 0 1
  8 ns 0000 0000 0 1 0 1

ちゃんと論理合成されるのか？

!2006-11-20 Mon

タイプ変換、conv_integer

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_unsigned.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006112000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006112000.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
      variable x  : std_logic_vector(7 downto 0);
    begin
      wait for 1 ns;
      x := "00001111"; write(lo, conv_integer(x));
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  15

!2006-11-19 Sun

タイプ変換、conv_std_logic_vector

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_arith.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006111900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111900.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, conv_std_logic_vector(512, 8), right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
   00000000

エラーやワーニングは出ないようだ

!2006-11-18 Sat

タイプ変換、conv_std_logic_vector

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use IEEE.std_logic_arith.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006111800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111800.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, conv_std_logic_vector(1, 8),   right, 9);
      write(lo, conv_std_logic_vector(255, 8), right, 9);
      write(lo, conv_std_logic_vector(-1, 8),  right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
   00000001 11111111 11111111

!2006-11-17 Fri

2006-11-16 で出力の関数を追加

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    type BYTE is array (7 downto 0) of std_logic;
    function "and" (A, B : in BYTE) return BYTE;
    procedure write(L: inout LINE; VALUE: in BYTE);
  end FOO;
  
  package body FOO is
    function "and" (A, B : in BYTE) return BYTE is
      variable x : std_logic_vector(7 downto 0);
      variable out_x : BYTE;
      begin
        for i in 0 to 7 loop
          x(i) := A(i) and B(i);
        end loop;
  
        out_x := x(7) & x(6) & x(5) & x(4) & x(3) & x(2) & x(1) & x(0);
        return out_x;
    end "and";
  
    procedure write(L: inout LINE; VALUE: in BYTE) is
      begin
        for i in 7 downto 0 loop
          write(L, VALUE(i), right, 1);
        end loop;
    end write;
  end FOO;
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  use WORK.FOO.all;
  
  entity AND2 is
    port (A, B:  in  BYTE;
          OUT_X: out BYTE);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_X <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:  in  BYTE;
            OUT_X: out BYTE);
    end component;
  
    signal IN_A, IN_B: BYTE;
    signal OUT_X:      BYTE;
    -- file outv : text is out "2006111700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111700.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "00001111"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "11110000"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4);
      write(lo, ' ', right, 1); write(lo, IN_A);
      write(lo, ' ', right, 1); write(lo, IN_B);
      write(lo, ' ', right, 1); write(lo, OUT_X);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00001111 00000001 00000001
  2 ns 11110000 00000001 00000000
  3 ns 11111111 11111111 11111111
  4 ns 11111111 11111111 11111111

!2006-11-16 Thu

2006-11-15 を loop を使って記述

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    type BYTE is array (7 downto 0) of std_logic;
    function "and" (A, B : in BYTE) return BYTE;
  end FOO;
  
  package body FOO is
    function "and" (A, B : in BYTE) return BYTE is
      variable x : std_logic_vector(7 downto 0);
      variable out_x : BYTE;
      begin
        for i in 0 to 7 loop
          x(i) := A(i) and B(i);
        end loop;
  
        out_x := x(7) & x(6) & x(5) & x(4) & x(3) & x(2) & x(1) & x(0);
        return out_x;
      end "and";
  end FOO;
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  use WORK.FOO.all;
  
  entity AND2 is
    port (A, B:  in  BYTE;
          OUT_X: out BYTE);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_X <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:  in  BYTE;
            OUT_X: out BYTE);
    end component;
  
    signal IN_A, IN_B: BYTE;
    signal OUT_X:      BYTE;
    -- file outv : text is out "2006111600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111600.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "00000001"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "00000001"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); -- write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
      --write(lo, IN_C, right, 2);
      --write(lo, OUT_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

!2006-11-15 Wed

オーバーロード

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    type BYTE is array (7 downto 0) of std_logic;
    function "and" (A, B : in BYTE) return BYTE;
  end FOO;
  
  package body FOO is
    function "and" (A, B : in BYTE) return BYTE is
      variable x0, x1, x2, x3, x4, x5, x6, x7 : std_logic;
      variable out_x : BYTE;
      begin
        x7 := A(7) and B(7);
        x6 := A(6) and B(6);
        x5 := A(5) and B(5);
        x4 := A(4) and B(4);
        x3 := A(3) and B(3);
        x2 := A(2) and B(2);
        x1 := A(1) and B(1);
        x0 := A(0) and B(0);
  
        out_x := x7 & x6 & x5 & x4 & x3 & x2 & x1 & x0;
        return out_x;
      end "and";
  end FOO;
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  use WORK.FOO.all;
  
  entity AND2 is
    port (A, B:  in  BYTE;
          OUT_X: out BYTE);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_X <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:  in  BYTE;
            OUT_X: out BYTE);
    end component;
  
    signal IN_A, IN_B: BYTE;
    signal OUT_X:      BYTE;
    -- file outv : text is out "2006111500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111500.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "00000001"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "00000001"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); -- write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
      --write(lo, IN_C, right, 2);
      --write(lo, OUT_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

!2006-11-14 Tue

オーバーロード

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    procedure foo(x : in std_logic; file outv : text);
    procedure foo(x : in std_logic_vector(7 downto 0); file outv : text);
  end FOO;
  
  package body FOO is
    procedure foo(x : in std_logic; file outv : text) is
      variable lo : line;
      begin
        write(lo, NOW, right, 4); write(lo, x, right, 2); writeline(outv, lo);
      end foo;
    procedure foo(x : in std_logic_vector(7 downto 0); file outv : text) is
      variable lo : line;
      begin
        write(lo, NOW, right, 4); write(lo, x, right, 9); writeline(outv, lo);
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006111400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111400.out";  -- VHDL '93
    signal OUT_X: std_logic;
  
  begin
    process
    begin
      foo('1', outv); wait for 1 ns;
      foo('0', outv); wait for 1 ns;
      foo("01010101", outv); wait for 1 ns;
    end process;
  
  end TESTBENCH;
で、
  0 ns 1
  1 ns 0
  2 ns 01010101

!2006-11-13 Mon

procedure

入力信号の singal を削除

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    procedure foo(x : in std_logic; signal out_x : out std_logic);
  end FOO;
  
  package body FOO is
    procedure foo(x : in std_logic; signal out_x : out std_logic) is
      begin
        out_x <= not x;
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006111300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111300.out";  -- VHDL '93
    signal OUT_X: std_logic;
  
  begin
    process
    begin
      foo('1', OUT_X); wait for 1 ns;
      foo('0', OUT_X); wait for 1 ns;
    end process;
  
    process
     variable lo : line;
    begin
      wait for 1 ns; write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 1

正しい記述かは不明

!2006-11-12 Sun

procedure

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    procedure foo(signal x : in std_logic; signal out_x : out std_logic);
  end FOO;
  
  package body FOO is
    procedure foo(signal x : in std_logic; signal out_x : out std_logic) is
      begin
        out_x <= not x;
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006111200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006111200.out";  -- VHDL '93
    signal IN_X:  std_logic;
    signal OUT_X: std_logic;
  
  begin
    foo(IN_X, OUT_X);
  
    process
    begin
      IN_X <= '1'; wait for 1 ns;
      IN_X <= '0'; wait for 1 ns;
    end process;
  
    process
     variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 2); write(lo, OUT_X, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0
  2 ns 0 1

!2006-11-11 Sat

procedure

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    procedure foo(x : in std_logic; file outv : text);
  end FOO;
  
  package body FOO is
    procedure foo(x : in std_logic; file outv : text) is
      variable lo : line;
      begin
        write(lo, NOW, right, 4); write(lo, x, right, 2); writeline(outv, lo);
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    file outv : text open WRITE_MODE is "2006111100.out";  -- VHDL '93
  
  begin
    process
    begin
      foo('1', outv); wait for 1 ns;
      foo('0', outv); wait for 1 ns;
    end process;
  
  end TESTBENCH;
で、
  0 ns 1
  1 ns 0
  2 ns 1

適当に書いてみたらできちゃった

!2006-11-10 Fri

procedure

  library IEEE;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  package FOO is
    procedure foo(x : in std_logic);
  end FOO;
  
  package body FOO is
    procedure foo(x : in std_logic) is
      file outv : text open WRITE_MODE is "2006111000.out";  -- VHDL '93
      variable lo : line;
      begin
        write(lo, NOW, right, 4); write(lo, x, right, 2); writeline(outv, lo);
      end foo;
  end FOO;
  
  library IEEE,STD;
  use IEEE.std_logic_1164.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
  begin
    process
    begin
      foo('1'); wait for 1 ns;
      foo('0'); wait for 1 ns;
    end process;
  
  end TESTBENCH;
で、
  2 ns 1

呼ぶたびに上書きされてしまうな…

!2006-11-09 Thu

順次 procedure

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    procedure foo(x : in std_logic; out_x : out std_logic);
  end FOO;
  
  package body FOO is
    procedure foo(x : in std_logic; out_x : out std_logic) is
      begin
        out_x := not x;
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006110900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110900.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
      variable OUT_X: std_logic;
    begin
      foo('1', OUT_X); wait for 1 ns; write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
      foo('0', OUT_X); wait for 1 ns; write(lo, NOW, right, 4); write(lo, OUT_X, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 1
  3 ns 0

!2006-11-08 Wed

function

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    function foo (x : std_logic) return std_logic;
  end FOO;
  
  package body FOO is
    function foo (x : std_logic) return std_logic is
      begin
        return not x;
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006110800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110800.out";  -- VHDL '93
    signal IN_X : std_logic;
  
  begin
    process
    begin
      IN_X <= '0'; wait for 2 ns;
      IN_X <= '1'; wait for 2 ns;
    end process;
  
    process
      variable lo : line;
      variable OUT_X: std_logic;
    begin
      OUT_X := foo(IN_X);
  
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 2); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 U
  2 ns 0 1
  3 ns 1 1
  4 ns 1 0
  5 ns 0 0

!2006-11-07 Tue

function

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    function foo (x : std_logic) return std_logic;
  end FOO;
  
  package body FOO is
    function foo (x : std_logic) return std_logic is
      begin
        return not x;
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006110700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110700.out";  -- VHDL '93
    signal OUT_X: std_logic;
  
  begin
    process
    begin
      OUT_X <= foo('1'); wait for 1 ns;
      OUT_X <= foo('0'); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 1
  3 ns 0

!2006-11-06 Mon

function

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    function foo (x : std_logic) return std_logic;
  end FOO;
  
  package body FOO is
    function foo (x : std_logic) return std_logic is
      begin
        return '0';
      end foo;
  end FOO;
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006110600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110600.out";  -- VHDL '93
    signal OUT_X: std_logic;
  
  begin
    process
    begin
      OUT_X <= foo('1');
      wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 0
  3 ns 0

* 引数は必ず必要っぽい(←二重表現？？？)

!2006-11-05 Sun

generate 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity fulladd is
    port (A, B, CIN: in  std_logic;
          Q, COUT:   out std_logic);
  end fulladd;
  
  architecture RTL of fulladd is
  begin
    Q    <= A xor B xor CIN;
    COUT <= (A and B) or (B and CIN) or (CIN and A);
  end RTL;
  
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity adder8 is
    port (A, B:  in  std_logic_vector(7 downto 0);
          OUT_X: out std_logic_vector(7 downto 0));
  end adder8;
  
  architecture RTL of adder8 is
    component fulladd
      port (A, B, CIN: in  std_logic;
            Q, COUT:   out std_logic);
    end component;
    signal tmp: std_logic_vector(8 downto 0);
  begin
    
    G: for i in 0 to 7 generate
      U: fulladd port map (A(i), B(i), tmp(i), OUT_X(i), tmp(i+1));
    end generate G;
  
    tmp(0) <= '0';
  
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component adder8
      port (A, B:  in  std_logic_vector(7 downto 0);
            OUT_X: out std_logic_vector(7 downto 0));
    end component;
  
    signal IN_A, IN_B : std_logic_vector(7 downto 0);
    signal OUT_Q:       std_logic_vector(7 downto 0);
    -- file outv : text is out "2006110500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110500.out";  -- VHDL '93
  
  begin
    DUT: adder8 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_Q
    );
  
    process
    begin
      IN_A <= "00000000"; IN_B <= "00000000"; wait for 1 ns;
      IN_A <= "00000001"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "00001111"; IN_B <= "00000001"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
      write(lo, OUT_Q, right, 9); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00000000 00000000 00000000
  2 ns 00000001 00000001 00000010
  3 ns 00001111 00000001 00010000

ラベルの省略はできないの？

!2006-11-04 Sat

ちょっと後で使うので、全加算器

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity fulladd is
    port (A, B, CIN: in  std_logic;
          Q, COUT:   out std_logic);
  end fulladd;
  
  architecture RTL of fulladd is
  begin
    Q    <= A xor B xor CIN;
    COUT <= (A and B) or (B and CIN) or (CIN and A);
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component fulladd
      port (A, B, CIN: in  std_logic;
            Q, COUT:   out std_logic);
    end component;
  
    signal IN_A, IN_B, CIN: std_logic;
    signal OUT_Q, COUT:     std_logic;
    -- file outv : text is out "2006110400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110400.out";  -- VHDL '93
  
  begin
    DUT: fulladd port map (
      A    => IN_A,
      B    => IN_B,
      CIN  => CIN,
      Q    => OUT_Q,
      COUT => COUT
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; CIN <= '0'; wait for 1 ns;
      IN_A <= '0'; IN_B <= '0'; CIN <= '1'; wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; CIN <= '0'; wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; CIN <= '1'; wait for 1 ns;
      IN_A <= '1'; IN_B <= '0'; CIN <= '0'; wait for 1 ns;
      IN_A <= '1'; IN_B <= '0'; CIN <= '1'; wait for 1 ns;
      IN_A <= '1'; IN_B <= '1'; CIN <= '0'; wait for 1 ns;
      IN_A <= '1'; IN_B <= '1'; CIN <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, CIN, right, 2);
      write(lo, COUT, right, 3); write(lo, OUT_Q, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0  0 0
  2 ns 0 0 1  0 1
  3 ns 0 1 0  0 1
  4 ns 0 1 1  1 0
  5 ns 1 0 0  0 1
  6 ns 1 0 1  1 0
  7 ns 1 1 0  1 0
  8 ns 1 1 1  1 1

!2006-11-03 Fri

ちょっと寄り道、verilog

2006-08-11, 2006-08-12 はこう書けば良かったのでは？
と、ふと。

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    adder8 iadder8(a, b, x);
  
    initial begin
            a <= 1; b <= 0;
      #STEP a <= 2; b <= 3;
      #STEP a <= 3; b <= 4;
      #STEP a <= 4; b <= 5;
      #STEP a <= 5; b <= 10;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h x=%h", a, b, x);
  
  endmodule
  
  module adder8(a, b, x);
    input  [7:0] a, b;
    output [7:0] x;
    wire   [8:0] tmp;
  
    generate
      genvar i;
      for (i = 0; i < 8; i = i + 1) begin
        fulladd fa(a[i], b[i], tmp[i], x[i], tmp[i+1]);
      end
    endgenerate
  
    assign tmp[0] = 1'b0;
  
  endmodule
  
  module fulladd(A, B, CIN, Q, COUT);
    input  A, B, CIN;
    output Q, COUT;
  
    assign Q = A ^ B ^ CIN;
    assign COUT = (A & B) | (B & CIN) | (CIN & A);
  
  endmodule
で、
  #          0 a=01 b=00 x=01
  #          1 a=02 b=03 x=05
  #          2 a=03 b=04 x=07
  #          3 a=04 b=05 x=09
  #          4 a=05 b=0a x=0f

!2006-11-02 Thu

遅延属性

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006110200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110200.out";  -- VHDL '93
    signal b  : BOOLEAN;
  
  begin
    process
    begin
      b <= FALSE; wait for 1 ns;
      b <= TRUE;  wait for 3 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, b, right, 6); write(lo, b'stable(2 ns), right, 6);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns FALSE  TRUE
  2 ns  TRUE FALSE
  3 ns  TRUE  TRUE
  4 ns  TRUE  TRUE
  5 ns FALSE FALSE
  6 ns  TRUE FALSE
  7 ns  TRUE  TRUE
  8 ns  TRUE  TRUE
  9 ns FALSE FALSE
  10 ns  TRUE FALSE

!2006-11-01 Wed

配列属性

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006110100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006110100.out";  -- VHDL '93
    signal IN_X  : std_logic_vector(7 downto 0);
  
  begin
    process
    begin
      IN_X <= "00000000"; wait for 1 ns;
      IN_X <= "11111111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, IN_X'left, right, 2); write(lo, IN_X'right, right, 2);
      write(lo, IN_X'high, right, 2); write(lo, IN_X'low, right, 2);
      -- write(lo, IN_X'range, right, 2); write(lo, IN_X'range_reverse, right, 2);
      write(lo, IN_X'length, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
   7 0 7 0 8

!2006-10-31 Tue

配列属性

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    subtype VECTOR8 is std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006103100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006103100.out";  -- VHDL '93
    signal IN_X  : VECTOR8;
  
  begin
    process
    begin
      IN_X <= VECTOR8'(7 downto 0 => '0'); wait for 1 ns;
      IN_X <= VECTOR8'(7 downto 0 => '1'); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, VECTOR8'left, right, 2); write(lo, VECTOR8'right, right, 2);
      write(lo, VECTOR8'high, right, 2); write(lo, VECTOR8'low, right, 2);
      -- write(lo, VECTOR8'range, right, 2); write(lo, VECTOR8'range_reverse, right, 2);
      write(lo, VECTOR8'length, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
   7 0 7 0 8

!2006-10-30 Mon

配列属性

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    subtype VECTOR8 is std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006103000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006103000.out";  -- VHDL '93
    signal IN_X  : VECTOR8;
  
  begin
    process
    begin
      IN_X <= VECTOR8'(7 downto 0 => '0'); wait for 1 ns;
      IN_X <= VECTOR8'(7 downto 0 => '1'); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, IN_X'left, right, 2); write(lo, IN_X'right, right, 2);
      write(lo, IN_X'high, right, 2); write(lo, IN_X'low, right, 2);
      -- write(lo, IN_X'range, right, 2); write(lo, IN_X'range_reverse, right, 2);
      write(lo, IN_X'length, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
   7 0 7 0 8

!2006-10-29 Sun

集合体

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    subtype VECTOR8 is std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006102900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102900.out";  -- VHDL '93
    signal IN_X  : VECTOR8;
  
  begin
    process
    begin
      IN_X <= VECTOR8'(1 to 7 => '0', 0 => '1'); wait for 1 ns;
      IN_X <= VECTOR8'(7 downto 0 => '1');       wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00000001
  2 ns 11111111

!2006-10-28 Sat

集合体

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    subtype VECTOR8 is std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006102800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102800.out";  -- VHDL '93
    signal IN_X  : VECTOR8;
  
  begin
    process
    begin
      IN_X <= VECTOR8'(2 => '0', 0 => '1', others => '0'); wait for 1 ns;
      IN_X <= VECTOR8'(others => '1');                     wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00000001
  2 ns 11111111

!2006-10-27 Fri

集合体

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    subtype VECTOR8 is std_logic_vector(7 downto 0);
  end FOO;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006102700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102700.out";  -- VHDL '93
    signal IN_X  : VECTOR8;
  
  begin
    process
    begin
      IN_X <= VECTOR8'('0', '0', '0', '0', '0', '0', '0', '1'); wait for 1 ns;
      IN_X <= VECTOR8'('1', '1', '1', '1', '1', '1', '1', '1'); wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00000001
  2 ns 11111111

「"0000"」といった感じでまとめて指定しようとしたら怒られてダメだったが、、、

!2006-10-26 Thu

スライス

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  
  entity FOO is
    port (IN_X:  in  std_logic_vector(7 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end FOO;
  
  architecture RTL of FOO is
  begin
    OUT_X <= IN_X(3 downto 0);
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component FOO
      port (IN_X:  in  std_logic_vector(7 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    -- file outv : text is out "2006102600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102600.out";  -- VHDL '93
    signal IN_X  : std_logic_vector(7 downto 0);
    signal OUT_X : std_logic_vector(3 downto 0);
  
  begin
    DUT: FOO port map (
      IN_X  => IN_X,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_X <= "11110000"; wait for 1 ns;
      IN_X <= "11110011"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_X, right, 9); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 11110000 0000
  2 ns 11110011 0011

「OUT_X <= IN_X(3 downto 0);」を「OUT_X <= IN_X(0 to 3);」にしたら
エラーとなりダメだった

!2006-10-25 Wed

文字列定数

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006102500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102500.out";  -- VHDL '93
  
  begin
    process
      variable lo : line;
      variable x : string(1 to 3);
    begin
      wait for 1 ns;
      x := "FOO"; write(lo, x);
      x := "BAR"; write(lo, x); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  FOOBAR

直接 write しようとしたら、怒られてしまいダメだった…

!2006-10-24 Tue

数値定数

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006102400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102400.out";  -- VHDL '93
    signal X: integer;
  
  begin
    process
    begin
      X <= 177;          wait for 1 ns;
      X <= 1_7_7;        wait for 1 ns;
      X <= 2#1011_0001#; wait for 1 ns;
      X <= 8#261#;       wait for 1 ns;
      X <= 16#B1#;       wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, X, right, 4); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 177
  2 ns 177
  3 ns 177
  4 ns 177
  5 ns 177

!2006-10-23 Mon

subtype

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    subtype VECTOR8 is std_logic_vector(7 downto 0);
  end FOO;
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  use WORK.FOO.all;
  
  entity AND2 is
    port (A, B:  in  VECTOR8;
          OUT_X: out VECTOR8);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_X <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:  in  VECTOR8;
            OUT_X: out VECTOR8);
    end component;
  
    signal IN_A, IN_B: VECTOR8;
    signal OUT_X:      VECTOR8;
    -- file outv : text is out "2006102300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102300.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "00001111"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11110000"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11110000"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "00001111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
      write(lo, OUT_X, right, 9); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00001111 11111111 00001111
  2 ns 11110000 11111111 11110000
  3 ns 11111111 11110000 11110000
  4 ns 11111111 00001111 00001111

これは色々継承してくれるようだ

!2006-10-22 Sun

配列タイプ 固定長

昨日のをループで書き直し。

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    type BYTE is array (7 downto 0) of std_logic;
  end FOO;
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  use WORK.FOO.all;
  
  entity AND2 is
    port (A, B:  in  BYTE;
          OUT_X: out BYTE);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    process (A, B) begin
      for i in 0 to 7 loop
        OUT_X(i) <= A(i) and B(i);
      end loop;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:  in  BYTE;
            OUT_X: out BYTE);
    end component;
  
    signal IN_A, IN_B: BYTE;
    signal OUT_X:      BYTE;
    -- file outv : text is out "2006102200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102200.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "00001111"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11110000"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11110000"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "00001111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4);
      write(lo, ' ', right, 1);
  
      for i in 0 to 7 loop
        write(lo, IN_A(7-i));
      end loop;
      write(lo, ' ', right, 1);
  
      for i in 0 to 7 loop
        write(lo, IN_B(7-i));
      end loop;
      write(lo, ' ', right, 1);
  
      for i in 0 to 7 loop
        write(lo, OUT_X(7-i));
      end loop;
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00001111 11111111 00001111
  2 ns 11110000 11111111 11110000
  3 ns 11111111 11110000 11110000
  4 ns 11111111 00001111 00001111

* 出力もできるようにしてみた。
* 全体の型を見て違いをはねるけど、要素ごとのアクセスができるのはなぜ？
* ループの範囲を減らすようにはできないの？？？(← downto で良かった…)

!2006-10-21 Sat

配列タイプ 固定長

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  package FOO is
    type BYTE is array (7 downto 0) of std_logic;
  end FOO;
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  use WORK.FOO.all;
  
  entity AND2 is
    port (A, B:  in  BYTE;
          OUT_X: out BYTE);
  end AND2;
  
  architecture RTL of AND2 is
    signal x0, x1, x2, x3, x4, x5, x6, x7 : std_logic;
  begin
    process (A, B) begin
      x7 <= A(7) and B(7);
      x6 <= A(6) and B(6);
      x5 <= A(5) and B(5);
      x4 <= A(4) and B(4);
      x3 <= A(3) and B(3);
      x2 <= A(2) and B(2);
      x1 <= A(1) and B(1);
      x0 <= A(0) and B(0);
  
      OUT_X <= x7 & x6 & x5 & x4 & x3 & x2 & x1 & x0;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:  in  BYTE;
            OUT_X: out BYTE);
    end component;
  
    signal IN_A, IN_B: BYTE;
    signal OUT_X:      BYTE;
    -- file outv : text is out "2006102100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102100.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "00000001"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "00000001"; IN_B <= "00000001"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); -- write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
      --write(lo, IN_C, right, 2);
      --write(lo, OUT_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

* 出力ができないよー
* ループ使えよ〜

!2006-10-20 Fri

整数タイプ定義

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006102000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006102000.out";  -- VHDL '93
  
  begin
    process
      type uchar is range 0 to 255;
  
      variable lo : line;
      variable x : uchar;
    begin
      wait for 1 ns;
      x := 255;
    end process;
  
  end TESTBENCH;

* 前、これが失敗していたのは、write でエラーが出ていたのかな？
* write できないと困るのだけど…。どうすれば？

!2006-10-19 Thu

type

  package FOO is
    type OPE is (ADD, SUB);
  end FOO;
  
  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_unsigned.ALL;
  use WORK.FOO.all;
  
  entity ALU is
    port (A, B:  in  std_logic_vector(7 downto 0);
          cmd:   in  OPE;
          OUT_X: out std_logic_vector(7 downto 0));
  end ALU;
  
  architecture RTL of ALU is
  begin
    process(A, B, cmd) begin
      if (cmd = ADD) then
        OUT_X <= A + B;
      else
        OUT_X <= A - B;
      end if;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  use WORK.FOO.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component ALU
      port (A, B:  in  std_logic_vector(7 downto 0);
            cmd:   in  OPE;
            OUT_X: out std_logic_vector(7 downto 0));
    end component;
  
    signal IN_A, IN_B: std_logic_vector(7 downto 0);
    signal IN_C:       OPE;
    signal OUT_X:      std_logic_vector(7 downto 0);
    -- file outv : text is out "2006101900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101900.out";  -- VHDL '93
  
  begin
    DUT: ALU port map (
      A     => IN_A,
      B     => IN_B,
      cmd   => IN_C,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "00000001"; IN_B <= "00000001"; IN_C <= ADD; wait for 1 ns;
      IN_A <= "00000001"; IN_B <= "00000001"; IN_C <= SUB; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; IN_C <= ADD; wait for 1 ns;
      IN_A <= "11111111"; IN_B <= "11111111"; IN_C <= SUB; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
      --write(lo, IN_C, right, 2);
      write(lo, OUT_X, right, 9); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 00000001 00000001 00000010
  2 ns 00000001 00000001 00000000
  3 ns 11111111 11111111 11111110
  4 ns 11111111 11111111 00000000

* package を導入しないと type が使えなかった。これで良いのだろうか？？？
* type を write で出力できなかった。定義する方法があるのか？？？

!2006-10-18 Wed

コンポーネント・インスタンス構文。ポート順に記述

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006101800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101800.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      IN_A,
      IN_B,
      OUT_AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;

!2006-10-17 Tue

generic 宣言(デフォルト値の入力)

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity ANDN is
    generic (N : integer := 7);
    port (A, B:    in  std_logic_vector(N downto 0);
          OUT_AND: out std_logic_vector(N downto 0));
  end ANDN;
  
  architecture RTL of ANDN is
  begin
      OUT_AND <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component ANDN
        generic (N : integer := 7);
        port (A, B:    in  std_logic_vector(N downto 0);
              OUT_AND: out std_logic_vector(N downto 0));
      end component;
  
      signal IN_A, IN_B: std_logic_vector(7 downto 0);
      signal OUT_AND:    std_logic_vector(7 downto 0);
      -- file outv : text is out "2006101700.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006101700.out";  -- VHDL '93
  
  begin
      DUT: ANDN
        port map (
          A       => IN_A,
          B       => IN_B,
          OUT_AND => OUT_AND
        );
  
      process
      begin
        IN_A <= "00000000"; IN_B <= "00000000"; wait for 1 ns;
        IN_A <= "11111111";                     wait for 1 ns;
        IN_A <= "00000000"; IN_B <= "11111111"; wait for 1 ns;
        IN_A <= "11111111";                     wait for 1 ns;
      end process;
  
      process
      variable lo : line;
      begin
        wait for 1 ns;
        write(lo, NOW, right, 4); write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
        write(lo, OUT_AND, right, 9); writeline(outv, lo);
      end process;
  
  end TESTBENCH;

!2006-10-16 Mon

generic 宣言

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity ANDN is
    generic (N : integer);
    port (A, B:    in  std_logic_vector(N downto 0);
          OUT_AND: out std_logic_vector(N downto 0));
  end ANDN;
  
  architecture RTL of ANDN is
  begin
      OUT_AND <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component ANDN
        generic (N : integer);
        port (A, B:    in  std_logic_vector(N downto 0);
              OUT_AND: out std_logic_vector(N downto 0));
      end component;
  
      signal IN_A, IN_B: std_logic_vector(7 downto 0);
      signal OUT_AND:    std_logic_vector(7 downto 0);
      -- file outv : text is out "2006101600.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006101600.out";  -- VHDL '93
  
  begin
      DUT: ANDN
        generic map (N => 7)
        port map (
          A       => IN_A,
          B       => IN_B,
          OUT_AND => OUT_AND
        );
  
      process
      begin
        IN_A <= "00000000"; IN_B <= "00000000"; wait for 1 ns;
        IN_A <= "11111111";                     wait for 1 ns;
        IN_A <= "00000000"; IN_B <= "11111111"; wait for 1 ns;
        IN_A <= "11111111";                     wait for 1 ns;
      end process;
  
      process
      variable lo : line;
      begin
        wait for 1 ns;
        write(lo, NOW, right, 4); write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
        write(lo, OUT_AND, right, 9); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  1 ns 00000000 00000000 00000000
  2 ns 11111111 00000000 00000000
  3 ns 00000000 11111111 00000000
  4 ns 11111111 11111111 11111111

!2006-10-15 Sun

assert 文

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A:  std_logic;
    -- file outv : text is out "2006101500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101500.out";  -- VHDL '93
  
  begin
    process
    begin
      assert IN_A = '1'
        report "IN_A = '1'"
        severity Warning;
  
      assert IN_A = '0'
        report "IN_A = '0'"
        severity Error;
  
      wait for 1 ns;
    end process;
  
    process
    begin
      IN_A <= '0'; wait for 1 ns;
      IN_A <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  # ** Warning: IN_A = '1'
  #    Time: 0 ns  Iteration: 0  Instance: /testbnch
  # ** Error: IN_A = '0'
  #    Time: 0 ns  Iteration: 0  Instance: /testbnch
  # ** Warning: IN_A = '1'
  #    Time: 1 ns  Iteration: 0  Instance: /testbnch
  # ** Error: IN_A = '0'
  #    Time: 2 ns  Iteration: 0  Instance: /testbnch
  # ** Warning: IN_A = '1'
  #    Time: 3 ns  Iteration: 0  Instance: /testbnch
  # ** Error: IN_A = '0'
  #    Time: 4 ns  Iteration: 0  Instance: /testbnch

!2006-10-14 Sat

wait 文。後置なし

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal OUT_X: std_logic;
    -- file outv : text is out "2006101400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101400.out";  -- VHDL '93
  
  begin
    process
    begin
      OUT_X <= '0'; wait for 1 ns;
      OUT_X <= '1'; wait for 1 ns;
      OUT_X <= '0'; wait for 1 ns;
      wait;
      OUT_X <= '1'; wait for 1 ns;
      OUT_X <= '0'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0
  2 ns 1
  3 ns 0
  4 ns 0
  5 ns 0
  6 ns 0

!2006-10-13 Fri

wait on 文

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A:  std_logic;
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006101300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101300.out";  -- VHDL '93
  
  begin
    process
    begin
      OUT_X <= "0000"; wait on IN_A;
      OUT_X <= "1111"; wait on IN_A;
    end process;
  
    process
    begin
      IN_A <= '0'; wait for 2 ns;
      IN_A <= '1'; wait for 2 ns;
      IN_A <= '0'; wait for 2 ns;
      IN_A <= '1'; wait for 2 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 1111
  2 ns 0 1111
  3 ns 1 0000
  4 ns 1 0000
  5 ns 0 1111
  6 ns 0 1111

!2006-10-12 Thu

wait until 文

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A:  std_logic;
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006101200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101200.out";  -- VHDL '93
  
  begin
    process
    begin
      OUT_X <= "0000";
      wait until IN_A = '1';
      OUT_X <= "1111";
      wait until IN_A = '0';
    end process;
  
    process
    begin
      IN_A <= '0'; wait for 2 ns;
      IN_A <= '1'; wait for 2 ns;
      IN_A <= '0'; wait for 2 ns;
      IN_A <= '1'; wait for 2 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0000
  2 ns 0 0000
  3 ns 1 1111
  4 ns 1 1111
  5 ns 0 0000
  6 ns 0 0000

!2006-10-11 Wed

exit 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity REVERSE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end REVERSE;
  
  architecture RTL of REVERSE is
  begin
    process(A)
    begin
      L: for i in 0 to 10 loop
        exit L when i = 4;
        OUT_X(3-i) <= A(i);
      end loop L;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component REVERSE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006101100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101100.out";  -- VHDL '93
  
  begin
    DUT: REVERSE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "0010"; wait for 1 ns;
      IN_A <= "0100"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1100"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 1111
  2 ns 0001 1000
  3 ns 0010 0100
  4 ns 0100 0010
  5 ns 1000 0001
  6 ns 1100 0011

!2006-10-10 Tue

next 文。ラベル使用

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity REVERSE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end REVERSE;
  
  architecture RTL of REVERSE is
  begin
    process(A)
    begin
      L: for i in 0 to 3 loop
        next L when i = 0;
        OUT_X(3-i) <= A(i);
      end loop L;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component REVERSE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006101000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006101000.out";  -- VHDL '93
  
  begin
    DUT: REVERSE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "0010"; wait for 1 ns;
      IN_A <= "0100"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1100"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 U111
  2 ns 0001 U000
  3 ns 0010 U100
  4 ns 0100 U010
  5 ns 1000 U001
  6 ns 1100 U011

!2006-10-09 Mon

next 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity REVERSE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end REVERSE;
  
  architecture RTL of REVERSE is
  begin
    process(A)
    begin
      L: for i in 0 to 3 loop
        next when i = 0;
        OUT_X(3-i) <= A(i);
      end loop L;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component REVERSE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006100900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100900.out";  -- VHDL '93
  
  begin
    DUT: REVERSE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "0010"; wait for 1 ns;
      IN_A <= "0100"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1100"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 U111
  2 ns 0001 U000
  3 ns 0010 U100
  4 ns 0100 U010
  5 ns 1000 U001
  6 ns 1100 U011

!2006-10-08 Sun

while 文

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A, IN_B:  std_logic_vector(3 downto 0);
    -- file outv : text is out "2006100800.out";  -- VHDL '87
    file fin  : text;
    file outv : text open WRITE_MODE is "2006100800.out";  -- VHDL '93
  
  begin
    process
      variable li : line;
      variable A, B : std_logic_vector(3 downto 0);
    begin
      file_open(fin, "2006100800.txt", READ_MODE);
      while (not endfile(fin)) loop
        readline(fin, li);
        read(li, A);
        read(li, B);
        IN_A <= A;
        IN_B <= B;
        wait for 1 ns;
      end loop;
      file_close(fin);
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 0000
  2 ns 0001 1000
  3 ns 0010 1100
  4 ns 0011 1110
  5 ns 0100 1111
  6 ns 0000 0000

!2006-10-07 Sat

while 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity REVERSE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end REVERSE;
  
  architecture RTL of REVERSE is
  begin
    process(A)
      variable i : integer := 0;
    begin
      while i < 3 loop
        OUT_X(3-i) <= A(i);
        i := i + 1;
      end loop;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component REVERSE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006100700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100700.out";  -- VHDL '93
  
  begin
    DUT: REVERSE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "0010"; wait for 1 ns;
      IN_A <= "0100"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1100"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 UUUU
  2 ns 0001 UUUU
  3 ns 0010 UUUU
  4 ns 0100 UUUU
  5 ns 1000 UUUU
  6 ns 1100 UUUU
ありゃ。ダメ

!2006-10-06 Fri

for 文。ラベル

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity REVERSE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end REVERSE;
  
  architecture RTL of REVERSE is
  begin
    process(A)
    begin
      L: for i in 0 to 3 loop
        OUT_X(3-i) <= A(i);
      end loop L;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component REVERSE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006100600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100600.out";  -- VHDL '93
  
  begin
    DUT: REVERSE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "0010"; wait for 1 ns;
      IN_A <= "0100"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1100"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;

!2006-10-05 Thu

for 文。downto

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity REVERSE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end REVERSE;
  
  architecture RTL of REVERSE is
  begin
    process(A)
    begin
      for i in 3 downto 0 loop
        OUT_X(3-i) <= A(i);
      end loop;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component REVERSE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006100500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100500.out";  -- VHDL '93
  
  begin
    DUT: REVERSE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "0010"; wait for 1 ns;
      IN_A <= "0100"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1100"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 1111
  2 ns 0001 1000
  3 ns 0010 0100
  4 ns 0100 0010
  5 ns 1000 0001
  6 ns 1100 0011

!2006-10-04 Wed

for 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity REVERSE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end REVERSE;
  
  architecture RTL of REVERSE is
  begin
    process(A)
    begin
      for i in 0 to 3 loop
        OUT_X(3-i) <= A(i);
      end loop;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component REVERSE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006100400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100400.out";  -- VHDL '93
  
  begin
    DUT: REVERSE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0001"; wait for 1 ns;
      IN_A <= "0010"; wait for 1 ns;
      IN_A <= "0100"; wait for 1 ns;
      IN_A <= "1000"; wait for 1 ns;
      IN_A <= "1100"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 1111
  2 ns 0001 1000
  3 ns 0010 0100
  4 ns 0100 0010
  5 ns 1000 0001
  6 ns 1100 0011

「process(A)」を「process」としたら、
「Possible infinite loop」とワーニングが出て、
確かに実行すると無限ループとなっているようで終了しなかった。

!2006-10-03 Tue

case 文。範囲指定

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  integer range 0 to 15;
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C is
        when 0 to 1 => OUT_SEL2 <= A;
        when 2 to 5 => OUT_SEL2 <= B;
        when others => OUT_SEL2 <= A and B;
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  integer range 0 to 15;
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       integer range 0 to 15;
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006100300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100300.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <=  1; wait for 1 ns;
                                IN_C <=  3; wait for 1 ns;
                                IN_C <=  5; wait for 1 ns;
                                IN_C <= 15; wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; IN_C <=  1; wait for 1 ns;
                                IN_C <=  3; wait for 1 ns;
                                IN_C <=  5; wait for 1 ns;
                                IN_C <= 15; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 3);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0  1 1
  2 ns 1 0  3 0
  3 ns 1 0  5 0
  4 ns 1 0 15 0
  5 ns 0 1  1 0
  6 ns 0 1  3 1
  7 ns 0 1  5 1
  8 ns 0 1 15 0

!2006-10-02 Mon

case 文。integer を式に

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  integer range 0 to 15;
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C is
        when 1 | 3 => OUT_SEL2 <= A;
        when 4 | 5 => OUT_SEL2 <= B;
        when others => OUT_SEL2 <= A and B;
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  integer range 0 to 15;
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       integer range 0 to 15;
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006100200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100200.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <=  1; wait for 1 ns;
                                IN_C <=  3; wait for 1 ns;
                                IN_C <=  4; wait for 1 ns;
                                IN_C <=  5; wait for 1 ns;
                                IN_C <= 15; wait for 1 ns;
                   IN_B <= '1'; IN_C <=  1; wait for 1 ns;
                                IN_C <=  3; wait for 1 ns;
                                IN_C <=  4; wait for 1 ns;
                                IN_C <=  5; wait for 1 ns;
                                IN_C <= 15; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 3);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0  1 1
  2 ns 1 0  3 1
  3 ns 1 0  4 0
  4 ns 1 0  5 0
  5 ns 1 0 15 0
  6 ns 1 1  1 1
  7 ns 1 1  3 1
  8 ns 1 1  4 1
  9 ns 1 1  5 1
  10 ns 1 1 15 1

ポートは、std_logic* でなくても良いのか〜

!2006-10-01 Sun

case 文。複数指定

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  std_logic_vector(3 downto 0);
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C is
        when "0001" | "0010" | "0011" => OUT_SEL2 <= A;
        when "0100" | "0101" => OUT_SEL2 <= B;
        when others => OUT_SEL2 <= A and B;
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  std_logic_vector(3 downto 0);
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       std_logic_vector(3 downto 0);
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006100100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006100100.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0010"; wait for 1 ns;
                                IN_C <= "0011"; wait for 1 ns;
                                IN_C <= "0100"; wait for 1 ns;
                                IN_C <= "0101"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
                   IN_B <= '1'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0011"; wait for 1 ns;
                                IN_C <= "0100"; wait for 1 ns;
                                IN_C <= "0101"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 5);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0 0001 1
  2 ns 1 0 0010 1
  3 ns 1 0 0011 1
  4 ns 1 0 0100 0
  5 ns 1 0 0101 0
  6 ns 1 0 1111 0
  7 ns 1 1 0001 1
  8 ns 1 1 0011 1
  9 ns 1 1 0100 1
  10 ns 1 1 0101 1
  11 ns 1 1 1111 1

!2006-09-30 Sat

case 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  std_logic_vector(3 downto 0);
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      case C is
        when "0001" => OUT_SEL2 <= A;
        when "0010" => OUT_SEL2 <= B;
        when others => OUT_SEL2 <= A and B;
      end case;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  std_logic_vector(3 downto 0);
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       std_logic_vector(3 downto 0);
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006093000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006093000.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
                   IN_B <= '1'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 5);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0 0001 1
  2 ns 1 0 0010 0
  3 ns 1 0 1111 0
  4 ns 1 1 0001 1
  5 ns 1 1 0010 1
  6 ns 1 1 1111 1

others はどんなときも省略できないらしい

!2006-09-29 Fri

if 文 again

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B:     in  std_logic;
          C:        in  std_logic_vector(3 downto 0);
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      if (C = "0001") then
        OUT_SEL2 <= A;
      elsif (C = "0010") then
        OUT_SEL2 <= B;
      else
        OUT_SEL2 <= A and B;
      end if;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B:     in  std_logic;
            C:        in  std_logic_vector(3 downto 0);
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal IN_C:       std_logic_vector(3 downto 0);
    signal OUT_SEL2:   std_logic;
    -- file outv : text is out "2006092900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092900.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '0'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
                   IN_B <= '1'; IN_C <= "0001"; wait for 1 ns;
                                IN_C <= "0010"; wait for 1 ns;
                                IN_C <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 5);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 0 0001 1
  2 ns 1 0 0010 0
  3 ns 1 0 1111 0
  4 ns 1 1 0001 1
  5 ns 1 1 0010 1
  6 ns 1 1 1111 1

!2006-09-28 Thu

if 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity SEL2 is
    port (A, B, C:  in  std_logic;
          OUT_SEL2: out std_logic);
  end SEL2;
  
  architecture RTL of SEL2 is
  begin
    process(A, B, C) begin
      if (C = '1') then
        OUT_SEL2 <= A;
      else
        OUT_SEL2 <= B;
      end if;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component SEL2
      port (A, B, C:  in  std_logic;
            OUT_SEL2: out std_logic);
    end component;
  
    signal IN_A, IN_B, IN_C: std_logic;
    signal OUT_SEL2:         std_logic;
    -- file outv : text is out "2006092800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092800.out";  -- VHDL '93
  
  begin
    DUT: SEL2 port map (
      A        => IN_A,
      B        => IN_B,
      C        => IN_C,
      OUT_SEL2 => OUT_SEL2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
      IN_A <= '1';              IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
      IN_A <= '1';              IN_C <= '0'; wait for 1 ns;
                                IN_C <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2); write(lo, IN_C, right, 2);
      write(lo, OUT_SEL2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0 0
  2 ns 0 0 1 0
  3 ns 1 0 0 0
  4 ns 1 0 1 1
  5 ns 0 1 0 1
  6 ns 0 1 1 0
  7 ns 1 1 0 1
  8 ns 1 1 1 1

条件のところに括弧は不要みたい

!2006-09-27 Wed

センシビティーリストに入れ忘れちゃったら？

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    process(B) begin
      OUT_AND2 <= A and B;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006092700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092700.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '1'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '0';              wait for 1 ns;
      IN_A <= '1'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '0';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1 1 1
  2 ns 0 1 1
  3 ns 1 0 0
  4 ns 0 0 0

!2006-09-26 Tue

process 文

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    process(A, B) begin
      OUT_AND2 <= A and B;
    end process;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006092600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092600.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1

「<=」の代りに「=」を書いたらダメだった。
うーん、良く分かっていなさ過ぎ〜

!2006-09-25 Mon

単項演算 -

  library IEEE;
  use IEEE.std_logic_1164.all;
  -- use IEEE.std_logic_arith.all;
  use IEEE.std_logic_signed.ALL;
  
  entity OPE is
    port (A:     in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(3 downto 0));
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_X <= - A;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A:     in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A:  std_logic_vector(3 downto 0);
    signal OUT_X: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006092500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092500.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A     => IN_A,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; wait for 1 ns;
      IN_A <= "0101"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, OUT_X, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 0001
  2 ns 0101 1011

IEEE.std_logic_unsigned.ALL だとコンパイルエラー

!2006-09-24 Sun

/, rem, mod, ** とばし

連接演算子

この記号を選んだか

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.ALL;
  
  entity OPE is
    port (A, B:  in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(7 downto 0));
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_X <= A & B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A, B:  in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(7 downto 0));
    end component;
  
    signal IN_A, IN_B: std_logic_vector(3 downto 0);
    signal OUT_X:      std_logic_vector(7 downto 0);
    -- file outv : text is out "2006092400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092400.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "1111"; IN_B <= "0000"; wait for 1 ns;
      IN_A <= "0101"; IN_B <= "1010"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      write(lo, OUT_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 1111 0000 11110000
  2 ns 0101 1010 01011010

!2006-09-23 Sat

乗算

  library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.ALL;
  
  entity OPE is
    port (A, B:  in  std_logic_vector(3 downto 0);
          OUT_X: out std_logic_vector(7 downto 0));
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_X <= A * B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A, B:  in  std_logic_vector(3 downto 0);
            OUT_X: out std_logic_vector(7 downto 0));
    end component;
  
    signal IN_A, IN_B: std_logic_vector(3 downto 0);
    signal OUT_X:      std_logic_vector(7 downto 0);
    -- file outv : text is out "2006092300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092300.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A     => IN_A,
      B     => IN_B,
      OUT_X => OUT_X
    );
  
    process
    begin
      IN_A <= "0001"; IN_B <= "0001"; wait for 1 ns;
      IN_A <= "0010"; IN_B <= "0010"; wait for 1 ns;
      IN_A <= "1000"; IN_B <= "0010"; wait for 1 ns;
      IN_A <= "1111"; IN_B <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      write(lo, OUT_X, right, 9);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0001 0001 00000001
  2 ns 0010 0010 00000100
  3 ns 1000 0010 00010000
  4 ns 1111 1111 11100001

* 出力が 8 ビットでないとシミュレーション時エラー
* 除算はどこに？

!2006-09-22 Fri

加算、減算

  library IEEE;
  use IEEE.std_logic_1164.all;
  -- use IEEE.std_logic_arith.all;
  use IEEE.std_logic_unsigned.ALL;
  
  entity OPE is
    port (A, B:           in  std_logic_vector(3 downto 0);
          OUT_X1, OUT_X2: out std_logic_vector(3 downto 0));
  end OPE;
  
  architecture RTL of OPE is
  begin
    OUT_X1 <= A + B;
    OUT_X2 <= A - B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OPE
      port (A, B:           in  std_logic_vector(3 downto 0);
            OUT_X1, OUT_X2: out std_logic_vector(3 downto 0));
    end component;
  
    signal IN_A, IN_B:     std_logic_vector(3 downto 0);
    signal OUT_X1, OUT_X2: std_logic_vector(3 downto 0);
    -- file outv : text is out "2006092200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092200.out";  -- VHDL '93
  
  begin
    DUT: OPE port map (
      A      => IN_A,
      B      => IN_B,
      OUT_X1 => OUT_X1,
      OUT_X2 => OUT_X2
    );
  
    process
    begin
      IN_A <= "0001"; IN_B <= "0001"; wait for 1 ns;
      IN_A <= "1000"; IN_B <= "0001"; wait for 1 ns;
      IN_A <= "1111"; IN_B <= "1111"; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      write(lo, OUT_X1, right, 5); write(lo, OUT_X2, right, 5);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で
  1 ns 0001 0001 0010 0000
  2 ns 1000 0001 1001 0111
  3 ns 1111 1111 1110 0000

Warning あり。理由不明

  use IEEE.std_logic_unsigned.ALL;
がないと、以下のエラー
  ** Error: 2006092200.vhdl(18): No feasible entries for infix operator "+".
  ** Error: 2006092200.vhdl(18): Type error resolving infix expression "+".
  ** Error: 2006092200.vhdl(19): No feasible entries for infix operator "-".
  ** Error: 2006092200.vhdl(19): Type error resolving infix expression "-".
  ** Error: 2006092200.vhdl(20): VHDL Compiler exiting

!2006-09-21 Thu

等価

  library IEEE;
  use IEEE.std_logic_1164.all;
  -- use IEEE.std_logic_unsigned.all;
  
  entity CMP is
    port (A, B: in std_logic_vector(3 downto 0);
          OUT_X1, OUT_X2: out std_logic);
  end CMP;
  
  architecture RTL of CMP is
  begin
    OUT_X1 <= '1' when A  = B else '0';
    OUT_X2 <= '1' when A /= B else '0';
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component CMP
      port (A, B: in std_logic_vector(3 downto 0);
            OUT_X1, OUT_X2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic_vector(3 downto 0);
    signal OUT_X1, OUT_X2: std_logic;
    -- file outv : text is out "2006092100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092100.out";  -- VHDL '93
  
  begin
    DUT: CMP port map (
      A      => IN_A,
      B      => IN_B,
      OUT_X1 => OUT_X1,
      OUT_X2 => OUT_X2
    );
  
    process
    begin
      IN_A <= "0000"; IN_B <= "0000"; wait for 1 ns;
      IN_A <= "1111";                 wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      write(lo, OUT_X1, right, 2); write(lo, OUT_X2, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 0000 1 0
  2 ns 1111 0000 0 1

!2006-09-20 Wed

比較

  library IEEE;
  use IEEE.std_logic_1164.all;
  -- use IEEE.std_logic_unsigned.all;
  
  entity CMP is
    port (A, B: in std_logic_vector(3 downto 0);
          OUT_X1, OUT_X2, OUT_X3, OUT_X4: out std_logic);
  end CMP;
  
  architecture RTL of CMP is
  begin
    OUT_X1 <= '1' when A >  B else '0';
    OUT_X2 <= '1' when A >= B else '0';
    OUT_X3 <= '1' when A <  B else '0';
    OUT_X4 <= '1' when A <= B else '0';
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component CMP
      port (A, B: in std_logic_vector(3 downto 0);
            OUT_X1, OUT_X2, OUT_X3, OUT_X4: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic_vector(3 downto 0);
    signal OUT_X1, OUT_X2, OUT_X3, OUT_X4: std_logic;
    -- file outv : text is out "2006092000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006092000.out";  -- VHDL '93
  
  begin
    DUT: CMP port map (
      A      => IN_A,
      B      => IN_B,
      OUT_X1 => OUT_X1,
      OUT_X2 => OUT_X2,
      OUT_X3 => OUT_X3,
      OUT_X4 => OUT_X4
    );
  
    process
    begin
      IN_A <= "0000"; IN_B <= "0000"; wait for 1 ns;
      IN_A <= "1111";                 wait for 1 ns;
      IN_A <= "0000"; IN_B <= "1111"; wait for 1 ns;
      IN_A <= "1111";                 wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 5); write(lo, IN_B, right, 5);
      write(lo, OUT_X1, right, 2); write(lo, OUT_X2, right, 2);
      write(lo, OUT_X3, right, 2); write(lo, OUT_X4, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0000 0000 0 1 0 1
  2 ns 1111 0000 1 1 0 0
  3 ns 0000 1111 0 0 1 1
  4 ns 1111 1111 0 1 0 1

* 比較結果を直接 std_logic に出せないのか？
* signed の比較とかもあるのかな？
* use IEEE.std_logic_unsigned.all; を入れたら何かワーニングを出していた

!2006-09-19 Tue

not

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity aNOT is
    port (A: in  std_logic;
          X: out std_logic);
  end aNOT;
  
  architecture RTL of aNOT is
  begin
    X <= not A;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component aNOT
      port (A: in  std_logic;
            X: out std_logic);
    end component;
  
    signal IN_A:  std_logic;
    signal OUT_X: std_logic;
    -- file outv : text is out "2006091900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091900.out";  -- VHDL '93
  
  begin
    DUT: aNOT port map (
      A => IN_A,
      X => OUT_X
    );
  
    process
    begin
      IN_A <= '0'; wait for 1 ns;
      IN_A <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2);
      write(lo, OUT_X, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 1
  2 ns 1 0

!2006-09-18 Mon

xor

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity XOR2 is
    port (A, B:     in  std_logic;
          OUT_XOR2: out std_logic);
  end XOR2;
  
  architecture RTL of XOR2 is
  begin
    OUT_XOR2 <= A xor B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component XOR2
      port (A, B:     in  std_logic;
            OUT_XOR2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_XOR2:   std_logic;
    -- file outv : text is out "2006091800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091800.out";  -- VHDL '93
  
  begin
    DUT: XOR2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_XOR2 => OUT_XOR2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_XOR2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 1
  3 ns 0 1 1
  4 ns 1 1 0

xnor はない？？？

!2006-09-17 Sun

nor

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity NOR2 is
    port (A, B:     in  std_logic;
          OUT_NOR2: out std_logic);
  end NOR2;
  
  architecture RTL of NOR2 is
  begin
    OUT_NOR2 <= A nor B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component NOR2
      port (A, B:     in  std_logic;
            OUT_NOR2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_NOR2:   std_logic;
    -- file outv : text is out "2006091700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091700.out";  -- VHDL '93
  
  begin
    DUT: NOR2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_NOR2 => OUT_NOR2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_NOR2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 1
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 0

!2006-09-16 Sat

or

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity OR2 is
    port (A, B:     in  std_logic;
          OUT_OR2: out std_logic);
  end OR2;
  
  architecture RTL of OR2 is
  begin
    OUT_OR2 <= A or B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component OR2
      port (A, B:     in  std_logic;
            OUT_OR2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_OR2:   std_logic;
    -- file outv : text is out "2006091600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091600.out";  -- VHDL '93
  
  begin
    DUT: OR2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_OR2 => OUT_OR2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_OR2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 1
  3 ns 0 1 1
  4 ns 1 1 1

!2006-09-15 Fri

nand

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity NAND2 is
    port (A, B:     in  std_logic;
          OUT_NAND2: out std_logic);
  end NAND2;
  
  architecture RTL of NAND2 is
  begin
    OUT_NAND2 <= A nand B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component NAND2
      port (A, B:     in  std_logic;
            OUT_NAND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_NAND2:   std_logic;
    -- file outv : text is out "2006091500.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091500.out";  -- VHDL '93
  
  begin
    DUT: NAND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_NAND2 => OUT_NAND2
    );
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_NAND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 1
  2 ns 1 0 1
  3 ns 0 1 1
  4 ns 1 1 0

!2006-09-14 Thu

when else
2009-09-09 改

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A, IN_B, IN_C: std_logic;
    signal IN_Z1, IN_Z2: boolean;
    signal OUT_X: std_logic;
    -- file outv : text is out "2006091400.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091400.out";  -- VHDL '93
  
  begin
    OUT_X <= IN_A when IN_Z1 else
             IN_B when IN_Z2 else IN_C;
  
    process
    begin
      IN_Z2 <= TRUE;
      IN_A <= '0'; IN_B <= '0'; IN_Z1 <= FALSE; wait for 1 ns;
                                IN_Z1 <= TRUE;  wait for 1 ns;
      IN_A <= '1';              IN_Z1 <= FALSE; wait for 1 ns;
                                IN_Z1 <= TRUE;  wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; IN_Z1 <= FALSE; wait for 1 ns;
                                IN_Z1 <= TRUE;  wait for 1 ns;
      IN_A <= '1';              IN_Z1 <= FALSE; wait for 1 ns;
                                IN_Z1 <= TRUE;  wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW,   right, 4);
      write(lo, IN_A,  right, 2);
      write(lo, IN_B,  right, 2);
      write(lo, IN_C,  right, 2);
      write(lo, IN_Z1, right, 6);
      write(lo, IN_Z2, right, 6);
      write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 U FALSE  TRUE 0
  2 ns 0 0 U  TRUE  TRUE 0
  3 ns 1 0 U FALSE  TRUE 0
  4 ns 1 0 U  TRUE  TRUE 1
  5 ns 0 1 U FALSE  TRUE 1
  6 ns 0 1 U  TRUE  TRUE 0
  7 ns 1 1 U FALSE  TRUE 1
  8 ns 1 1 U  TRUE  TRUE 1

!2006-09-13 Wed

variable でシフトレジスタっぽい記述

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal A: std_logic;
    -- file outv : text is out "2006091300.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091300.out";  -- VHDL '93
  
  begin
    process
    begin
      A <= '0'; wait for 1 ns;
      A <= '1'; wait for 1 ns;
    end process;
  
    process
      variable B, C, D: std_logic;
      variable lo : line;
    begin
      -- wait until A'event and A = '1';
      wait until A'event;
      B := A;
      C := B;
      D := C;
  
      write(lo, NOW, right, 4);
      write(lo, A, right, 2); write(lo, B, right, 2); write(lo, C, right, 2); write(lo, D, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  0 ns 0 0 0 0
  1 ns 1 1 1 1
  2 ns 0 0 0 0
  3 ns 1 1 1 1
  4 ns 0 0 0 0
  5 ns 1 1 1 1
  6 ns 0 0 0 0
  7 ns 1 1 1 1
  8 ns 0 0 0 0

!2006-09-12 Tue

signal でシフトレジスタっぽい記述

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal A, B, C, D: std_logic;
    -- file outv : text is out "2006091200.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091200.out";  -- VHDL '93
  
  begin
    process
    begin
      -- wait until A'event and A = '1';
      wait until A'event;
      B <= A;
      C <= B;
      D <= C;
    end process;
  
    process
    begin
      A <= '0'; wait for 1 ns;
      A <= '1'; wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4);
      write(lo, A, right, 2); write(lo, B, right, 2); write(lo, C, right, 2); write(lo, D, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 U U
  2 ns 1 1 0 U
  3 ns 0 0 1 0
  4 ns 1 1 0 1
  5 ns 0 0 1 0
  6 ns 1 1 0 1
  7 ns 0 0 1 0
  8 ns 1 1 0 1

!2006-09-11 Mon

after

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
    port (A, B:     in  std_logic;
          OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
    OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    component AND2
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
    end component;
  
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006091100.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091100.out";  -- VHDL '93
  
  begin
    DUT: AND2 port map (
      A        => IN_A,
      B        => IN_B,
      OUT_AND2 => OUT_AND2
    );
  
    process
    begin
      IN_A <= '0',
              '1' after 1 ns,
              '0' after 2 ns,
              '1' after 3 ns;
      IN_B <= '0',
              '1' after 2 ns;
      wait for 4 ns;
    end process;
  
    process
      variable lo : line;
    begin
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
      wait for 1 ns;
    end process;
  
  end TESTBENCH;
で、
  0 ns U U U
  1 ns 1 0 0
  2 ns 0 1 0
  3 ns 1 1 0
  4 ns 1 1 1
？

!2006-09-10 Sun

きまぐれに process 内に書いてみる。

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006091000.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006091000.out";  -- VHDL '93
  
  begin
    process
    begin
      OUT_AND2 <= (IN_A and IN_B); wait for 1 ns;
    end process;
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 U
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 0
  5 ns 0 0 1

どう解釈すれば？
wait を入れないと、無限ループしちゃうみたいだし…。

!2006-09-09 Sat

条件信号代入文

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A, IN_B: std_logic;
    signal IN_Z: boolean;
    signal OUT_X: std_logic;
    -- file outv : text is out "2006090900.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006090900.out";  -- VHDL '93
  
  begin
    OUT_X <= IN_A when IN_Z else IN_B;
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; IN_Z <= FALSE; wait for 1 ns;
                                IN_Z <= TRUE;  wait for 1 ns;
      IN_A <= '1';              IN_Z <= FALSE; wait for 1 ns;
                                IN_Z <= TRUE;  wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; IN_Z <= FALSE; wait for 1 ns;
                                IN_Z <= TRUE;  wait for 1 ns;
      IN_A <= '1';              IN_Z <= FALSE; wait for 1 ns;
                                IN_Z <= TRUE;  wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW,   right, 4);
      write(lo, IN_A,  right, 2);
      write(lo, IN_B,  right, 2);
      write(lo, IN_Z,  right, 6);
      write(lo, OUT_X, right, 2);
      writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 FALSE 0
  2 ns 0 0  TRUE 0
  3 ns 1 0 FALSE 0
  4 ns 1 0  TRUE 1
  5 ns 0 1 FALSE 1
  6 ns 0 1  TRUE 0
  7 ns 1 1 FALSE 1
  8 ns 1 1  TRUE 1

!2006-09-08 Fri

代入文と after

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006090800.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006090800.out";  -- VHDL '93
  
  begin
    OUT_AND2 <= (IN_A and IN_B) after 1 ns;
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1
  5 ns 0 0 0
？
    OUT_AND2 <= (IN_A and IN_B) after 2 ns;
  
      IN_A <= '1';              wait for 2 ns;
と変更してみたら変化があったが、
いまいちタイミングが良く分からない。
波形で見れば分かるのかな？？？

!2006-09-07 Thu

architecture の中に直接論理式を書いてみる

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    signal IN_A, IN_B: std_logic;
    signal OUT_AND2:   std_logic;
    -- file outv : text is out "2006090700.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006090700.out";  -- VHDL '93
  
  begin
    OUT_AND2 <= IN_A and IN_B;
  
    process
    begin
      IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
      IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
      IN_A <= '1';              wait for 1 ns;
    end process;
  
    process
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
      write(lo, OUT_AND2, right, 2); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1

!2006-09-06 Wed

constant

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
    -- file outv : text is out "2006090600.out";  -- VHDL '87
    file outv : text open WRITE_MODE is "2006090600.out";  -- VHDL '93
  
  begin
    process
      constant x1 : integer := 1;
      constant x2 : boolean  := true;
  
      variable lo : line;
    begin
      wait for 1 ns;
      write(lo, x1, right, 2); write(lo, x2, right, 5); writeline(outv, lo);
    end process;
  
  end TESTBENCH;
で、
   1 TRUE

!2006-09-05 Tue

BIT と std_logic

BIT は二値らしい。
VHDL って大文字、小文字区別ないんだっけ？？？

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006090500.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006090500.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable b1 : BIT;
      variable b2 : std_logic;
      begin
        wait for 1 ns;
        b1 := '1'; write(lo, b1);
        b2 := '0'; write(lo, b2, right, 2); writeline(outv, lo);
  
        -- b1 := 'X'; write(lo, b1); -- ** Error: 2006090500.vhdl(28): Incompatible types for variable assignment.
        b2 := 'X'; write(lo, b2, right, 2); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  1 0
   X

!2006-09-04 Mon

BIT_VECTOR

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006090400.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006090400.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable v1 : BIT_VECTOR(1 to 8);
      variable v2 : BIT_VECTOR(7 downto 0);
      begin
        wait for 1 ns;
        v1 := "01010101";
        v2 := "10101010";
        write(lo, v1); write(lo, v2, right, 9); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  01010101 10101010

!2006-09-03 Sun

STRING

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006090300.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006090300.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable s  : STRING(1 to 7);
      begin
        wait for 1 ns;
        -- s := "foo"; -- ** Error: 2006090300.vhdl(24): Expected length is 7; string length is 3.
        s := "foo bar";
        write(lo, s); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  foo bar

文字数が足りないとダメらしい。

!2006-09-02 Sat

POSITIVE

使うのかな？

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006090200.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006090200.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable i  : POSITIVE;
      begin
        wait for 1 ns;
        write(lo, 1, right, 4); i := 256;
        write(lo, i, right, 4);
        -- i := 0; -- ** Error: 2006090200.vhdl(26): (vcom-1144) Value 0 is out of range 1 to 2147483647.
        writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
     1 256

!2006-09-01 Fri

NATURAL

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006090100.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006090100.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable i  : NATURAL;
      begin
        wait for 1 ns;
        write(lo, 1, right, 4); i := 256;
        write(lo, i, right, 4);
        -- i := -1;  -- ** Error: 2006090100.vhdl(26): (vcom-1144) Value -1 is out of range 0 to 2147483647.
        writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
     1 256
     1 256

!2006-08-31 Thu

INTEGER

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006083100.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006083100.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable i  : INTEGER;
      begin
        wait for 1 ns;
        write(lo, 1, right, 4); i := 256;
        write(lo, i, right, 4);
        writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
     1 256
     1 256

!2006-08-30 Wed

CHARACTER

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006083000.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006083000.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable c  : CHARACTER;
      begin
        wait for 1 ns;
        write(lo, 'A', right, 2);
        write(lo, 'B', right, 2); c := 'C';
        write(lo, c,   right, 2);
        writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
   A B C
   A B C

!2006-08-29 Tue

BOOLEAN -> std_logic

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity BOOLEAN2STD_LOGIC is
      port (A:     in  BOOLEAN;
            OUT_A: out std_logic);
  end BOOLEAN2STD_LOGIC;
  
  architecture RTL of BOOLEAN2STD_LOGIC is
  begin
    OUT_A <= '1' when A else '0';
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component BOOLEAN2STD_LOGIC
        port (A:     in  BOOLEAN;
              OUT_A: out std_logic);
      end component;
  
      signal IN_A  : BOOLEAN;
      signal OUT_A : std_logic;
      -- file outv : text is out "2006082900.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082900.out";  -- VHDL '93
  
  begin
      DUT: BOOLEAN2STD_LOGIC port map (
        A     => IN_A,
        OUT_A => OUT_A
      );
  
      process
      begin
        IN_A <= TRUE;  wait for 1 ns;
        IN_A <= FALSE; wait for 1 ns;
      end process;
  
      process
      variable lo   : line;
      begin
        wait for 1 ns;
  
        write(lo, OUT_A, right, 4); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
     1
     0

!2006-08-28 Mon

BOOLEAN -> BIT
回路っぽく分けるつもりはなかったのだが、
直接 process の中に書くとエラーになってしまったので…。

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity BOOLEAN2BIT is
      port (A:     in  BOOLEAN;
            OUT_A: out BIT);
  end BOOLEAN2BIT;
  
  architecture RTL of BOOLEAN2BIT is
  begin
    OUT_A <= '1' when A else '0';
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component BOOLEAN2BIT
        port (A:     in  BOOLEAN;
              OUT_A: out BIT);
      end component;
  
      signal IN_A  : BOOLEAN;
      signal OUT_A : BIT;
      -- file outv : text is out "2006082800.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082800.out";  -- VHDL '93
  
  begin
      DUT: BOOLEAN2BIT port map (
        A     => IN_A,
        OUT_A => OUT_A
      );
  
      process
      begin
        IN_A <= TRUE;  wait for 1 ns;
        IN_A <= FALSE; wait for 1 ns;
      end process;
  
      process
      variable lo   : line;
      begin
        wait for 1 ns;
  
        write(lo, OUT_A, right, 4); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
     1
     0

!2006-08-27 Sun

BOOLEAN

  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      -- file outv : text is out "2006082700.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082700.out";  -- VHDL '93
  
  begin
      process
      variable lo : line;
      variable b  : BOOLEAN;
      begin
        wait for 1 ns;
        write(lo, TRUE, right, 5); write(lo, FALSE, right, 6);
  
        b := TRUE;  write(lo, b, right, 5);
        b := FALSE; write(lo, b, right, 6);
        writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
   TRUE FALSE TRUE FALSE
   TRUE FALSE TRUE FALSE

!2006-08-26 Sat

BIT データタイプ

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic_vector(11 downto 0);
            OUT_AND2: out std_logic_vector(11 downto 0));
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic_vector(11 downto 0);
                OUT_AND2: out std_logic_vector(11 downto 0));
      end component;
  
      signal IN_A, IN_B: std_logic_vector(11 downto 0);
      signal OUT_AND2:   std_logic_vector(11 downto 0);
      -- file outv : text is out "2006082600.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082600.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      begin
          IN_A <=  "000000000000";   IN_B <= "000000000000"; wait for 1 ns;
          IN_A <= B"1111_1111_1111";                         wait for 1 ns;
          IN_A <= X"000";            IN_B <= "111111111111"; wait for 1 ns;
          IN_A <= O"7777";                                   wait for 1 ns;
      end process;
  
      process
      variable lo : line;
      begin
          wait for 1 ns;
          write(lo, NOW, right, 4); write(lo, IN_A, right, 13); write(lo, IN_B, right, 13);
          write(lo, OUT_AND2, right, 13); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  1 ns 000000000000 000000000000 000000000000
  2 ns 111111111111 000000000000 000000000000
  3 ns 000000000000 111111111111 000000000000
  4 ns 111111111111 111111111111 111111111111

B をつけた場合のみ、「_」を含んでも良いのか？？？

!2006-08-25 Fri

std_logic_vector

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic_vector(7 downto 0);
            OUT_AND2: out std_logic_vector(7 downto 0));
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic_vector(7 downto 0);
                OUT_AND2: out std_logic_vector(7 downto 0));
      end component;
  
      signal IN_A, IN_B: std_logic_vector(7 downto 0);
      signal OUT_AND2:   std_logic_vector(7 downto 0);
      -- file outv : text is out "2006082500.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082500.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      begin
          IN_A <= "00000000"; IN_B <= "00000000"; wait for 1 ns;
          IN_A <= "11111111";                     wait for 1 ns;
          IN_A <= "00000000"; IN_B <= "11111111"; wait for 1 ns;
          IN_A <= "11111111";                     wait for 1 ns;
      end process;
  
      process
      variable lo : line;
      begin
          wait for 1 ns;
          write(lo, NOW, right, 4); write(lo, IN_A, right, 9); write(lo, IN_B, right, 9);
          write(lo, OUT_AND2, right, 9); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  1 ns 00000000 00000000 00000000
  2 ns 11111111 00000000 00000000
  3 ns 00000000 11111111 00000000
  4 ns 11111111 11111111 11111111

!2006-08-24 Thu

2006-08-22 で wait の位置を変えてみる

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic;
                OUT_AND2: out std_logic);
      end component;
  
      signal IN_A, IN_B: std_logic;
      signal OUT_AND2:   std_logic;
      -- file outv : text is out "2006082400.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082400.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      begin
          IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
          IN_A <= '1';              wait for 1 ns;
          IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
          IN_A <= '1';              wait for 1 ns;
      end process;
  
      process
      variable lo : line;
      begin
          wait for 1 ns;
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
      end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1

!2006-08-23 Wed

入力と結果出力を分けてみる。
入力サイクルを 10ns にして。

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic;
                OUT_AND2: out std_logic);
      end component;
  
      signal IN_A, IN_B: std_logic;
      signal OUT_AND2:   std_logic;
      -- file outv : text is out "2006082300.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082300.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      begin
        IN_A <= '0'; IN_B <= '0'; wait for 10 ns;
        IN_A <= '1';              wait for 10 ns;
        IN_A <= '0'; IN_B <= '1'; wait for 10 ns;
        IN_A <= '1';              wait for 10 ns;
      end process;
  
      process
      variable lo : line;
      begin
        wait for 1 ns;
  
        while TRUE loop
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
          wait for 10 ns;
        end loop;
      end process;
  
  end TESTBENCH;
で、
  1 ns 0 0 0
  11 ns 1 0 0
  21 ns 0 1 0
  31 ns 1 1 1

桁を簡単にそろえる方法はないのかなあ〜

!2006-08-22 Tue

入力と結果出力を分けてみる

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic;
                OUT_AND2: out std_logic);
      end component;
  
      signal IN_A, IN_B: std_logic;
      signal OUT_AND2:   std_logic;
      -- file outv : text is out "2006082200.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082200.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      begin
          IN_A <= '0'; IN_B <= '0'; wait for 1 ns;
          IN_A <= '1';              wait for 1 ns;
          IN_A <= '0'; IN_B <= '1'; wait for 1 ns;
          IN_A <= '1';              wait for 1 ns;
      end process;
  
      process
      variable lo : line;
      begin
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
          wait for 1 ns;
      end process;
  
  end TESTBENCH;
で、
  0 ns U U U
  1 ns 0 0 0
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1

!2006-08-21 Mon

出力まわりの模索

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic;
                OUT_AND2: out std_logic);
      end component;
  
      signal IN_A, IN_B: std_logic;
      signal OUT_AND2:   std_logic;
      -- file outv : text is out "2006082100.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082100.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      variable lo : line;
      begin
          IN_A <= '0'; IN_B <= '0';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns; IN_A <= '1';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns; IN_A <= '0'; IN_B <= '1';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns; IN_A <= '1';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns;
  end process;
  
  end TESTBENCH;
で、
  0 ns U U U
  1 ns 0 0 0
  2 ns 1 0 0
  3 ns 0 1 0
  4 ns 1 1 1

!2006-08-20 Sun

  library IEEE;
  use IEEE.std_logic_1164.all;
  
  entity AND2 is
      port (A, B:     in  std_logic;
            OUT_AND2: out std_logic);
  end AND2;
  
  architecture RTL of AND2 is
  begin
      OUT_AND2 <= A and B;
  end RTL;
  
  
  library IEEE,STD;
  use STD.TEXTIO.all;
  use IEEE.std_logic_1164.all;
  use IEEE.std_logic_textio.all;
  
  entity TESTBNCH is
  end TESTBNCH;
  
  architecture TESTBENCH of TESTBNCH is
      component AND2
          port (A, B:     in  std_logic;
                OUT_AND2: out std_logic);
      end component;
  
      signal IN_A, IN_B: std_logic;
      signal OUT_AND2:   std_logic;
      -- file outv : text is out "2006082000.out";  -- VHDL '87
      file outv : text open WRITE_MODE is "2006082000.out";  -- VHDL '93
  
  begin
      DUT: AND2 port map (
        A        => IN_A,
        B        => IN_B,
        OUT_AND2 => OUT_AND2
      );
  
      process
      variable lo : line;
      begin
          IN_A <= '0'; IN_B <= '0';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns;
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 9 ns; IN_A <= '1';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns;
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 9 ns; IN_A <= '0'; IN_B <= '1';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns;
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 9 ns; IN_A <= '1';
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait for 1 ns;
          write(lo, NOW, right, 4); write(lo, IN_A, right, 2); write(lo, IN_B, right, 2);
          write(lo, OUT_AND2, right, 2); writeline(outv, lo);
  
          wait;
  end process;
  
  end TESTBENCH;
で、
  0 ns U U U
  1 ns 0 0 0
  10 ns 0 0 0
  11 ns 1 0 0
  20 ns 1 0 0
  21 ns 0 1 0
  30 ns 0 1 0
  31 ns 1 1 1

途中に再度 library 記述をしないとエラーになった。
そんなもんなのだろうか？
無理してひとつのファイルに書こうとするからいけないのだが。

!2006-08-19 Sat

Verilog 2001 まとめ

* configuration  は、使い方 不明
* アトリビュート は、使い方 不明
* ファイルI/O は、2006-07-15 以前に既に一部試し済み(fgetc, fgets, fscanf, sscanf)。あとは、スキップ

!2006-08-18 Fri

再入可能なタスク

  // kaitei nyumon Verilog HDL kijutsu p.249
  
  module testbench;
  
    task automatic disp;
      input integer n;
      begin
              $display("time=%0d  n=%0d", $stime, n);
        #1000 $display("time=%0d n=%0d", $stime, n);
      end
    endtask
  
    initial begin
      #100 disp(1364);
    end
  
    initial begin
      #500 disp(2001);
  
      $finish;
    end
  
  endmodule
で、
  # time=100  n=1364
  # time=500  n=2001
  # time=1100 n=1364
  # time=1500 n=2001

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-17 Thu

再帰

  // kaitei nyumon Verilog HDL kijutsu p.248
  module testbench;
    reg  [7:0] a;
  
    parameter STEP = 1;
  
    function automatic integer fact;
      input [7:0] n;
  
      begin
        if (n <= 1)
          fact = 1;
        else
          fact = n * fact(n-1);
      end
  
    endfunction
  
    initial begin
            a <= 8'h00;
      #STEP a <= fact(1);
      #STEP a <= fact(2);
      #STEP a <= fact(3);
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h", a);
    end
  
  endmodule
で、
  #          0 a=00
  #          1 a=01
  #          2 a=02
  #          3 a=06

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-16 Wed

定数関数 again

  module testbench;
    reg  [7:0] a;
  
    parameter STEP = 1;
  
    function integer f;
      input [7:0] i;
  
      f = i + 1;
  
    endfunction
  
    initial begin
              a <= 8'h00;
      #(f(9)) a <= 8'h01;
      #(f(9))
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h", a);
    end
  
  endmodule
で、
                     0 a=00
                    10 a=01

Icarus, modelsim とも OK。
ただし、括弧で囲わないとダメだった

もしかしたら、定数関数の例になっていないかも。
というのも、遅延には変数も書けるみたいだから。

!2006-08-15 Tue

定数関数 again

  module testbench;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = {f(7){1'h1}};
  
    function integer f;
      input [7:0] i;
  
      f = i + 1;
  
    endfunction
  
    initial begin
      #STEP
      #STEP
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
  #          0 x=ff

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-14 Mon

定数関数 again

  module testbench;
    reg  [7:0] a;
  
    parameter STEP = f(9);
  
    function integer f;
      input [7:0] i;
  
      f = i + 1;
  
    endfunction
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h01;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h", a);
    end
  
  endmodule
で、
  #          0 a=00
  #         10 a=01

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-13 Sun

定数関数 again

  module testbench;
    reg  [f(6):0] a;
  
    parameter STEP = 1;
  
    function integer f;
      input [7:0] i;
  
      f = i + 1;
  
    endfunction
  
    initial begin
            a <= 8'h00;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h", a);
    end
  
  endmodule

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-12 Sat

generate

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    adder8 iadder8(a, b, x);
  
    initial begin
            a <= 1; b <= 0;
      #STEP a <= 2; b <= 3;
      #STEP a <= 3; b <= 4;
      #STEP a <= 4; b <= 5;
      #STEP a <= 5; b <= 10;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h x=%h", a, b, x);
  
  endmodule
  
  module adder8(a, b, x);
    input  [7:0] a, b;
    output [7:0] x;
    wire   [7:0] tmp;
  
    generate
      genvar i;
      for (i = 0; i < 8; i = i + 1) begin
        if (i == 0)
          fulladd fa(a[0], b[0], 1'b0, x[0], tmp[0]);
        else
          fulladd fa(a[i], b[i], tmp[i-1], x[i], tmp[i]);
      end
    endgenerate
  
  endmodule
  
  module fulladd(A, B, CIN, Q, COUT);
    input  A, B, CIN;
    output Q, COUT;
  
    assign Q = A ^ B ^ CIN;
    assign COUT = (A & B) | (B & CIN) | (CIN & A);
  
  endmodule
で、
  #          0 a=01 b=00 x=01
  #          1 a=02 b=03 x=05
  #          2 a=03 b=04 x=07
  #          3 a=04 b=05 x=09
  #          4 a=05 b=0a x=0f

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-11 Fri

generate

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    adder8 iadder8(a, b, x);
  
    initial begin
            a <= 1; b <= 0;
      #STEP a <= 2; b <= 3;
      #STEP a <= 3; b <= 4;
      #STEP a <= 4; b <= 5;
      #STEP a <= 5; b <= 10;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h x=%h", a, b, x);
  
  endmodule
  
  module adder8(a, b, x);
    input  [7:0] a, b;
    output [7:0] x;
    wire   [7:0] tmp;
  
    fulladd fa(a[0], b[0], 1'b0, x[0], tmp[0]);
  
    generate
      genvar i;
      for (i = 1; i < 8; i = i + 1) begin
        fulladd fa(a[i], b[i], tmp[i-1], x[i], tmp[i]);
      end
    endgenerate
  
  endmodule
  
  module fulladd(A, B, CIN, Q, COUT);
    input  A, B, CIN;
    output Q, COUT;
  
    assign Q = A ^ B ^ CIN;
    assign COUT = (A & B) | (B & CIN) | (CIN & A);
  
  endmodule
で、
  #          0 a=01 b=00 x=01
  #          1 a=02 b=03 x=05
  #          2 a=03 b=04 x=07
  #          3 a=04 b=05 x=09
  #          4 a=05 b=0a x=0f

* Icarus だとコンパイルエラー
* modelsim は OK
  
  fulladd fa(a[0], b[0], 1'b0, x[0], tmp[0]);
を
  fulladd fa(a[0], b[0], 0, x[0], tmp[0]);
としたら、
  [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'CIN'.

!2006-08-10 Thu

generate

  module testbench;
    reg  [7:0] a;
    wire [7:0] x0, x1;
  
    parameter STEP = 1;
  
    test #0 it0(a, x0);
    test #1 it1(a, x1);
  
    initial begin
            a <= 1;
      #STEP a <= 2;
      #STEP a <= 3;
      #STEP a <= 4;
      #STEP a <= 5;
      #STEP a <= 6;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h x0=%h x1=%h", a, x0, x1);
  
  endmodule
  
  module test(i, x);
    input  [7:0] i;
    output [7:0] x;
  
    parameter c = 1;
  
    generate
      if (c == 1) begin
        assign x = i + 1;
      end else begin
        assign x = i - 1;
      end
    endgenerate
  
  endmodule
で、
  #          0 a=01 x0=00 x1=02
  #          1 a=02 x0=01 x1=03
  #          2 a=03 x0=02 x1=04
  #          3 a=04 x0=03 x1=05
  #          4 a=05 x0=04 x1=06
  #          5 a=06 x0=05 x1=07

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-09 Wed

ベクタの部分選択記述

  module testbench;
    reg  [7:0] a, x;
    wire [2:0] tmp = a[x -: 3];
  
    parameter STEP = 1;
  
    initial begin
            a <= 8'b1110_1101;
            x <= 2;
      #STEP x <= 3;
      #STEP x <= 4;
      #STEP x <= 5;
      #STEP x <= 6;
      #STEP x <= 7;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%b x=%h tmp=%b", a, x, tmp);
  
  endmodule
で、
  #          0 a=11101101 x=02 tmp=101
  #          1 a=11101101 x=03 tmp=110
  #          2 a=11101101 x=04 tmp=011
  #          3 a=11101101 x=05 tmp=101
  #          4 a=11101101 x=06 tmp=110
  #          5 a=11101101 x=07 tmp=111

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-08 Tue

ベクタの部分選択記述

  module testbench;
    reg  [7:0] a, x;
    wire [2:0] tmp = a[x +: 3];
  
    parameter STEP = 1;
  
    initial begin
            a <= 8'b1110_1101;
            x <= 0;
      #STEP x <= 1;
      #STEP x <= 2;
      #STEP x <= 3;
      #STEP x <= 4;
      #STEP x <= 5;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%b x=%h tmp=%b", a, x, tmp);
  
  endmodule
で、
  #          0 a=11101101 x=00 tmp=101
  #          1 a=11101101 x=01 tmp=110
  #          2 a=11101101 x=02 tmp=011
  #          3 a=11101101 x=03 tmp=101
  #          4 a=11101101 x=04 tmp=110
  #          5 a=11101101 x=05 tmp=111

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-07 Mon

配列の部分選択、ビット選択

  module testbench;
    reg  [7:0]  a, b;
    wire [15:0] x;
    reg  [15:0] data[1][0:256];
    wire [7:0]  tmp = data[0][2][11:4];
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;     data[0][0] <= x;
      #STEP a <= 1;     b <= 8'hfc; data[0][1] <= x;
      #STEP a <= 8'h80; b <= 8'hfd; data[0][2] <= x;
      #STEP a <= 8'hff; b <= 8'hfe; data[0][3] <= x;
      #STEP a <= 8'hff; b <= 8'hff; data[0][4] <= x;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%b b=%b  sum=%b tmp=%b", a, b, x, tmp);
  
  endmodule
で、
  #          0 a=00000000 b=00000000  sum=0000000000000000 tmp=xxxxxxxx
  #         10 a=00000001 b=11111100  sum=0000000011111101 tmp=xxxxxxxx
  #         20 a=10000000 b=11111101  sum=0000000101111101 tmp=00001111
  #         30 a=11111111 b=11111110  sum=0000000111111101 tmp=00001111
  #         40 a=11111111 b=11111111  sum=0000000111111110 tmp=00001111

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-06 Sun

配列の部分選択、ビット選択

  module testbench;
    reg  [7:0]  a, b;
    wire [15:0] x;
    reg  [15:0] data[0:256];
    wire [7:0]  tmp = data[2][11:4];
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;     data[0] <= x;
      #STEP a <= 1;     b <= 8'hfc; data[1] <= x;
      #STEP a <= 8'h80; b <= 8'hfd; data[2] <= x;
      #STEP a <= 8'hff; b <= 8'hfe; data[3] <= x;
      #STEP a <= 8'hff; b <= 8'hff; data[4] <= x;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%b b=%b  sum=%b tmp=%b", a, b, x, tmp);
  
  endmodule
で、
  #          0 a=00000000 b=00000000  sum=0000000000000000 tmp=xxxxxxxx
  #         10 a=00000001 b=11111100  sum=0000000011111101 tmp=xxxxxxxx
  #         20 a=10000000 b=11111101  sum=0000000101111101 tmp=00001111
  #         30 a=11111111 b=11111110  sum=0000000111111101 tmp=00001111
  #         40 a=11111111 b=11111111  sum=0000000111111110 tmp=00001111

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-05 Sat

多次元配列

  module testbench;
    reg  [7:0]  a, b;
    wire [7:0]  x;
    reg  [15:0] data[1][0:256];
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;     data[0][0] <= x;
      #STEP a <= 1;     b <= 5;     data[0][1] <= x;
      #STEP a <= 8'h80; b <= 1;     data[0][2] <= x;
      #STEP a <= 8'hff; b <= 1;     data[0][3] <= x;
      #STEP a <= 8'hff; b <= 8'hff; data[0][4] <= x;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule

* readmemh は 2次元をサポートしていないらしい
* Icarus だとコンパイルエラー

!2006-08-04 Fri

定数関数。定数関数の例になっていない可能性ありまくり。

  module testbench;
    reg  [7:0] a;
  
    parameter STEP = 1;
  
    function integer f;
      input [7:0] i;
  
      f = i + 1;
  
    endfunction
  
    initial begin
            a <= 8'h00;
      #STEP a <= f(1);
      #STEP a <= f(2);
      #STEP a <= f(3);
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h", a);
    end
  
  endmodule
で、
                     0 a=00
                     1 a=02
                     2 a=03
                     3 a=04

!2006-08-03 Thu

sformat

  module testbench;
    reg  [7:0] a;
    reg  [64*8:1] str;
  
    parameter STEP = 2;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h08;
      #STEP a <= 8'h80;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    always #(STEP/2) begin
      $sformat(str, " a=%d", a);
      $display("%s", str);
    end
  
  endmodule
で、
  #                                                            a=  0
  #                                                            a=  0
  #                                                            a=  8
  #                                                            a=  8
  #                                                            a=128
  #                                                            a=128
  #                                                            a=255

* Icarus だとコンパイル OK, 実行エラー
* modelsim は OK

!2006-08-02 Wed

継続的代入文のデフォルトネット宣言

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
    assign y = a - b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h x=%h", a, b, x);
    end
  
  endmodule
で、
  #          0 a=00 b=00 x=00
  #          1 a=01 b=05 x=06
  #          2 a=80 b=01 x=81
  #          3 a=ff b=01 x=00
  #          4 a=ff b=ff x=fe

* Icarus だとコンパイルエラー
* modelsim は OK

!2006-08-01 Tue

  module testbench;
    wire signed [7:0] x;
  
    parameter STEP = 1;
  
    assign x = -1;
  
    initial begin
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " x=%h", x);
    end
  
  endmodule
で、
                     0 x=03
singed 指定なしでも、同じ結果

modelsim だと、
  #          0 x=ff

何を検査していたか忘れた

!2006-07-31 Mon

32ビットを超えるビットの自動拡張

  module testbench;
    wire [63:0] x;
  
    parameter STEP = 1;
  
    assign x = 'hzzzzzzzz;
  
    initial begin
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " x=%h", x);
    end
  
  endmodule
で、
                     0 x=zzzzzzzzzzzzzzzz

良く分からず。これは、2001 風の出力？？？

!2006-07-30 Sun

「$unsigned」

  module testbench;
    reg  [7:0] a;
  
    parameter STEP = 1;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h08;
      #STEP a <= 8'h80;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%d", $unsigned(a));
    end
  
  endmodule
で、
                     0 a=  0
                     1 a=  8
                     2 a=128
                     3 a=255

!2006-07-29 Sat

「$signed」

  module testbench;
    reg  [7:0] a;
  
    parameter STEP = 1;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h08;
      #STEP a <= 8'h80;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%d", $signed(a));
    end
  
  endmodule
で、
  #          0 a=   0
  #          1 a=   8
  #          2 a=-128
  #          3 a=  -1

* Icarus だとコンパイル OK、実行 -> セグメンテーション違反
* modelsim は OK

!2006-07-28 Fri

符合付きシフト。符号関係ある？

  module testbench;
    reg  [7:0] a;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a <<< 1;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h08;
      #STEP a <= 8'h80;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h  out=%b", a, x);
    end
  
  endmodule
で、
                     0 a=00  out=00000000
                     1 a=08  out=00010000
                     2 a=80  out=00000000
                     3 a=ff  out=11111110

!2006-07-27 Thu

符合付きシフト

  module testbench;
    reg  [7:0] a;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a >>> 1;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h08;
      #STEP a <= 8'h80;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h  out=%b", a, x);
    end
  
  endmodule
で、
                     0 a=00  out=00000000
                     1 a=08  out=00000100
                     2 a=80  out=11000000
                     3 a=ff  out=11111111

!2006-07-26 Wed

符合付き整数

  module testbench;
    wire x;
  
    parameter STEP = 1;
  
    assign x = 8'sh00 > 8'shff;
  
    initial begin
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " out=%b", x);
    end
  
  endmodule
で、
                     0 out=1

  module testbench;
    wire x;
  
    parameter STEP = 1;
  
    assign x = 8'h00 > 8'shff;
  
    initial begin
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " out=%b", x);
    end
  
  endmodule
で、
                     0 out=0

!2006-07-25 Tue

符合付き演算

  module testbench;
    reg  signed [7:0] a, b;
    wire signed [7:0] f;
    wire              x;
  
    parameter STEP = 1;
  
    assign f = fun(b);
    assign x = a > f;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 8'hff;
      #STEP a <= 8'h80; b <= 0;
      #STEP a <= 8'hff; b <= 1;
      #STEP
      $finish;
    end
  
    function signed [7:0] fun;
      input  [7:0] x;
  
      fun = x;
  
    endfunction
  
    initial begin
      $monitor($stime, " a=%h b=%h  out=%b", a, b, x);
    end
  
  endmodule

* Icarus だとコンパイルエラー
* modelsim は OK
* function に singed がつけれると嬉しいの？？？

!2006-07-24 Mon

符合付き演算

  module testbench;
    reg  signed [7:0] a, b;
    wire              x;
  
    parameter STEP = 1;
  
    assign x = a > b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 8'hff;
      #STEP a <= 8'h80; b <= 0;
      #STEP a <= 8'hff; b <= 1;
      #STEP
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  out=%b", a, b, x);
    end
  
  endmodule
で、
                     0 a=00 b=00  out=0
                     1 a=01 b=ff  out=1
                     2 a=80 b=00  out=0
                     3 a=ff b=01  out=0

signed を取って実行すると、
                     0 a=00 b=00  out=0
                     1 a=01 b=ff  out=0
                     2 a=80 b=00  out=1
                     3 a=ff b=01  out=1

!2006-07-23 Sun

default_nettype

  `default_nettype wire
  
  module testbench;
    reg  [7:0] a, b, c;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, c, x);
  
    initial begin
            a <= 0; b <= 0; c <= 0;
      #STEP a <= 1; b <= 3; c <= 5;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h c=%h  sum=%h", a, b, c, x);
  
  endmodule
  
  module top(a, b, c, x);
    input  [7:0] a, b, c;
    output [7:0] x;
  
    assign tmp = a + b;
    assign x   = tmp + c;
  
  endmodule
で、
  #          0 a=00 b=00 c=00  sum=00
  #          1 a=01 b=03 c=05  sum=05

Icarus だとコンパイルエラー

none にすると、

  `default_nettype none
  
  module testbench;
    reg  [7:0] a, b, c;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, c, x);
  
    initial begin
            a <= 0; b <= 0; c <= 0;
      #STEP a <= 1; b <= 3; c <= 5;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h c=%h  sum=%h", a, b, c, x);
  
  endmodule
  
  module top(a, b, c, x);
    input  [7:0] a, b, c;
    output [7:0] x;
  
    assign tmp = a + b;
    assign x   = tmp + c;
  
  endmodule

modelsim でも正しくエラー

!2006-07-22 Sat

undef

  `define FOO
  
  `undef FOO
  
  `ifdef FOO
  `define S 10
  `else
  `define S 1
  `endif
  
  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = `S;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule

!2006-07-21 Fri

ifndef

  `define FOO
  
  `ifndef FOO
  `define S 10
  `else
  `define S 1
  `endif
  
  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = `S;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule

!2006-07-20 Thu

ANSI-C 形式のポートリスト

  module testbench;
    reg  [7:0]  a, b;
    wire [7:0]  x;
  
    parameter STEP = 1;
  
    sum isum(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module sum(
    input  [7:0] a,
    input  [7:0] b,
    output [7:0] x
    );
  
    assign x = a + b;
  
  endmodule

* 最後に , をつけると、Icarus   はコンパイル ×
* 最後に , をつけると、modelsim はワーニング

!2006-07-19 Wed

reg 初期値

  module testbench;
    reg  [7:0] a = 0, b = 0;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
      #STEP
      #STEP
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

!2006-07-18 Tue

ポート宣言 + データタイプ宣言

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  wire [7:0] a;
    input  wire [7:0] b;
    output reg  [7:0] x;
  
    always @* begin
      x <= a + b;
    end
  
  endmodule
で、
                     0 a1=00 b1=00 a2=0000 b2=0000  sum1=00 sum2=0000
                     1 a1=01 b1=05 a2=0001 b2=0005  sum1=06 sum2=0006
                     2 a1=80 b1=01 a2=8000 b2=0001  sum1=81 sum2=8001
                     3 a1=ff b1=01 a2=ffff b2=0001  sum1=00 sum2=0000

!2006-07-17 Mon

インライン・パラメータ。これで OK?

  module testbench;
    reg  [7:0]  a1, b1;
    reg  [15:0] a2, b2;
    wire [7:0]  x1;
    wire [15:0] x2;
  
    parameter STEP = 1;
  
    sum #(.width1(8), .width2(16)) isum(a1, b1, x1, a2, b2, x2);
  
    initial begin
            a1 <= 0;     b1 <= 0;     a2 <= 0;        b2 <= 0;
      #STEP a1 <= 1;     b1 <= 5;     a2 <= 1;        b2 <= 5;
      #STEP a1 <= 8'h80; b1 <= 1;     a2 <= 16'h8000; b2 <= 1;
      #STEP a1 <= 8'hff; b1 <= 1;     a2 <= 16'hffff; b2 <= 1;
      #STEP a1 <= 8'hff; b1 <= 8'hff; a2 <= 16'hffff; b2 <= 16'hffff;
      $finish;
    end
  
    initial $monitor($stime, " a1=%h b1=%h a2=%h b2=%h  sum1=%h sum2=%h",
                     a1, b1, a2, b2, x1, x2);
  
  endmodule
  
  module sum(a1, b1, x1, a2, b2, x2);
    parameter width1 = 8;
    parameter width2 = 16;
    input  [width1-1:0] a1, b1;
    input  [width2-1:0] a2, b2;
    output [width1-1:0] x1;
    output [width2-1:0] x2;
  
    assign x1 = a1 + b1;
    assign x2 = a2 + b2;
  
  endmodule

!2006-07-16 Sun

冪乗

  module testbench;
    reg  [2**3-1:0] a, b;
    wire [2**3-1:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule

* Icarus では、コンパイルエラー
* modelsim では、OK

!2006-07-15 Sat

「@*」

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
    reg    [7:0] x;
  
    always @* begin
      x <= a + b;
    end
  
  endmodule

!2006-07-14 Fri

dumpfile, dumpvars

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $dumpfile("2006071400.vcd");
      $dumpvars(0, testbench);
    end
  
  endmodule

gtkwave で見たところ、3ns までしか表示されなかった？？？

!2006-07-13 Thu

event 型

  module testbench;
    event      x;
    reg  [7:0] y;
  
    parameter STEP = 10;
  
    initial begin
      #STEP
      #STEP
      #STEP -> x;
      #STEP
      #STEP
      $finish;
    end
  
    initial begin
      @(x) y <= 8'hff;
    end
  
    always #(STEP/2) $display ($stime, " x=%h  y=%h", x, y);
  
  endmodule
で、
                     5 x=
  ERROR: Incompatible value: %h
    y=xx
                    10 x=
  ERROR: Incompatible value: %h
    y=xx
                    15 x=
  ERROR: Incompatible value: %h
    y=xx
                    20 x=
  ERROR: Incompatible value: %h
    y=xx
                    25 x=
  ERROR: Incompatible value: %h
    y=xx
                    30 x=
  ERROR: Incompatible value: %h
    y=xx
                    35 x=
  ERROR: Incompatible value: %h
    y=ff
                    40 x=
  ERROR: Incompatible value: %h
    y=ff
                    45 x=
  ERROR: Incompatible value: %h
    y=ff

y の値の方は大丈夫みたい

!2006-07-12 Wed

wire 宣言をしないと、1 ビット wire とされるらしい

  module testbench;
    reg  [7:0] a, b, c;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, c, x);
  
    initial begin
            a <= 0; b <= 0; c <= 0;
      #STEP a <= 1; b <= 3; c <= 5;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h c=%h  sum=%h", a, b, c, x);
  
  endmodule
  
  module top(a, b, c, x);
    input  [7:0] a, b, c;
    output [7:0] x;
  
    assign tmp = a + b;
    assign x   = tmp + c;
  
  endmodule
で、
  #          0 a=00 b=00 c=00  sum=00
  #          1 a=01 b=03 c=05  sum=05

* Icarus では、コンパイルエラー
* modelsim では、OK (ただし、tmp は 1bit wire)

!2006-07-11 Tue

reg の宣言の仕方

http://park11.wakwak.com/~nkon/diy/verilog/memo.html
を見ていて、2006-05-07 のダメさに気がついた…。

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
    reg    [7:0] x;
  
    always @(a or b) begin
      x <= a + b;
    end
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

!2006-07-10 Mon

task again

  module testbench;
    reg  [7:0] x, xx;
  
    parameter STEP = 10;
  
    task task1;
      input  [7:0] ix;
  
      begin
        #20  xx = ix;
      end
  
    endtask
  
    initial begin
            x <= 0; task1(x);
      #STEP x <= 1; task1(x);
      #STEP x <= 2; task1(x);
      #STEP x <= 3; task1(x);
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h  xx=%h", x, xx);
  
  endmodule
で、
                     0 x=00  xx=xx
                    30 x=01  xx=xx
                    50 x=01  xx=00
                    60 x=02  xx=00
                    80 x=02  xx=01
                    90 x=03  xx=01
                   110 x=03  xx=02

!2006-07-09 Sun

wait

  module testbench;
    reg  [7:0] x, y;
  
    parameter STEP = 10;
  
    initial begin
            x <= 0;
      #STEP
      #STEP
      #STEP x <= 1;
      #STEP
      #STEP
      $finish;
    end
  
    initial begin
      wait (x) y <= 8'hff;
    end
  
    always #(STEP/2) $display ($stime, " x=%h  y=%h", x, y);
  
  endmodule
で、
                     5 x=00  y=xx
                    10 x=00  y=xx
                    15 x=00  y=xx
                    20 x=00  y=xx
                    25 x=00  y=xx
                    30 x=00  y=xx
                    35 x=01  y=ff
                    40 x=01  y=ff
                    45 x=01  y=ff

回路として wait を書いた場合、論理合成できるのだろうか？

!2006-07-08 Sat

sscanf

  module testbench;
    reg [7:0] x1, x2, x3;
  
    parameter STEP = 10;
    integer r;
  
    initial begin
            r = $sscanf("1 2 3", "%d %d %d", x1, x2, x3);
      #STEP r = $sscanf("4 5 6", "%d %d %d", x1, x2, x3);
  
      #STEP $finish;
    end
  
    initial $monitor($stime, " x1=%d x2=%d x3=%d", x1, x2, x3);
  
  endmodule
で、
  #          0 x1=  1 x2=  2 x3=  3
  #         10 x1=  4 x2=  5 x3=  6

Icarus では、実行時エラー。実装されていないみたい。

!2006-07-07 Fri

fscanf

  `define TEXT_FILE "2006070700.txt"
  
  module testbench;
    reg [7:0]    x1, x2, x3;
  
    parameter STEP = 10;
    integer fd, r;
  
    initial begin
      fd = $fopen(`TEXT_FILE, "r");
  
            r = $fscanf(fd, "%d %d %d", x1, x2, x3);
      #STEP r = $fscanf(fd, "%d %d %d", x1, x2, x3);
  
      $fclose(fd);
      #STEP $finish;
    end
  
    initial $monitor($stime, " x1=%d x2=%d x3=%d", x1, x2, x3);
  
  endmodule

2006070700.txt は、
  1 2 3
  4 5 6
で、
  #          0 x1=  1 x2=  2 x3=  3
  #         10 x1=  4 x2=  5 x3=  6

Icarus では、実行時エラー。実装されていないみたい。

!2006-07-06 Thu

fgets

  `define TEXT_FILE "2006070600.txt"
  
  module testbench;
    reg  [16*8:1] str;
  
    parameter STEP = 10;
    integer fd, r;
  
    initial begin
      fd = $fopen(`TEXT_FILE, "r");
  
            r = $fgets(str, fd);
      #STEP r = $fgets(str, fd);
  
      $fclose(fd);
      #STEP $finish;
    end
  
    initial $monitor($stime, " str=%s", str);
  
  endmodule

2006070600.txt は、
  foo
  bar
で、
                     0 str=            foo
  
                    10 str=            bar
  

fgets からの値を受け取らないと、なぜか実行時エラーになった
(少なくとも Icarus では)

!2006-07-05 Wed

fgetc

  `define TEXT_FILE "2006070500.txt"
  
  module testbench;
    reg  [7:0]  a;
  
    parameter STEP = 10;
    integer fd;
  
    initial begin
      fd = $fopen(`TEXT_FILE, "r");
  
            a <= $fgetc(fd);
      #STEP a <= $fgetc(fd);
      #STEP a <= $fgetc(fd);
      #STEP a <= $fgetc(fd);
      #STEP a <= $fgetc(fd);
  
      $fclose(fd);
      #STEP $finish;
    end
  
    initial $monitor($stime, " a=%x", a);
  
  endmodule
2006070500.txt は、
  0123456789
で、
                     0 a=30
                    10 a=31
                    20 a=32
                    30 a=33
                    40 a=34

!2006-07-04 Tue

writememb

  module testbench;
    reg  [7:0]  a, b;
    wire [7:0]  x;
    reg  [7:0] data[0:31];
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;     data[0] <= x;
      #STEP a <= 1;     b <= 5;     data[1] <= x;
      #STEP a <= 8'h80; b <= 1;     data[2] <= x;
      #STEP a <= 8'hff; b <= 1;     data[3] <= x;
      #STEP a <= 8'hff; b <= 8'hff; data[4] <= x;
  
      $writememb("2006070400.txt", data);
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
で、
  // 0x00000000
  xxxxxxxx
  00000000
  00000110
  10000001
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  xxxxxxxx
  ...

!2006-07-03 Mon

writememh

  module testbench;
    reg  [7:0]  a, b;
    wire [7:0]  x;
    reg  [7:0] data[0:31];
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;     data[0] <= x;
      #STEP a <= 1;     b <= 5;     data[1] <= x;
      #STEP a <= 8'h80; b <= 1;     data[2] <= x;
      #STEP a <= 8'hff; b <= 1;     data[3] <= x;
      #STEP a <= 8'hff; b <= 8'hff; data[4] <= x;
  
      $writememh("2006070300.txt", data);
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
で、
  // 0x00000000
  xx
  00
  06
  81
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  // 0x00000010
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx
  xx

!2006-07-02 Sun

task。
一応実行できたが、良く分かっていない…。
どういうときに使うべきかも良く分かっていない…。

  module testbench;
    reg  [7:0] x, xx;
  
    parameter STEP = 10;
  
    task task1;
      input  [7:0] xx;
      output [7:0] yy;
      //reg    [7:0] yy;
  
      begin
        #20  yy = xx;
      end
  
    endtask
  
    initial begin
            x <= 0; task1(x, xx);
      #STEP x <= 1; task1(x, xx);
      #STEP x <= 2; task1(x, xx);
      #STEP x <= 3; task1(x, xx);
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h  xx=%h", x, xx);
  
  endmodule
で、
                     0 x=00  xx=xx
                    30 x=01  xx=xx
                    50 x=01  xx=00
                    60 x=02  xx=00
                    80 x=02  xx=01
                    90 x=03  xx=01
                   110 x=03  xx=02

おっと、a.out をはじめて見てみたが、先頭は
  #! /usr/bin/vvp
だった。なんか変だとは思っていたんだよ〜。

シミュレータのマシンコードが書いてあるわけか。。。

!2006-07-01 Sat

ifdef

  `define FOO
  
  `ifdef FOO
  `define S 10
  `else
  `define S 1
  `endif
  
  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = `S;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                    10 a=01 b=05  sum=06
                    20 a=80 b=01  sum=81
                    30 a=ff b=01  sum=00

「`default_nettype」「`*unconnected*」「`signed」「`unsigned」とばし。

!2006-06-30 Fri

include

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    `include "2006063001.v"
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule

2006063001.v は、
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end

(短く済まそうとしたら)良い例にはならなかった…。

!2006-06-29 Thu

define。引数が使えたとは、はじめて知った…

  `define bw(w) #(w)
  
  module testbench;
    reg  [7:0]  a1, b1;
    wire [7:0]  x1;
  
    parameter STEP = 1;
  
    sum `bw(8) isum(a1, b1, x1);
  
    initial begin
            a1 <= 0;     b1 <= 0;
      #STEP a1 <= 1;     b1 <= 5;
      #STEP a1 <= 8'h80; b1 <= 1;
      #STEP a1 <= 8'hff; b1 <= 1;
      #STEP a1 <= 8'hff; b1 <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a1=%h b1=%h  sum1=%h", a1, b1, x1);
  
  endmodule
  
  module sum(a, b, x);
    parameter width = 8;
    input  [width-1:0] a;
    input  [width-1:0] b;
    output [width-1:0] x;
  
    assign x = a + b;
  
  endmodule

* 余り良い例が思い浮かばなかった
* Icarus ではコンパイルできなかった

!2006-06-28 Wed

「`reset_all」とばし。
* Google で検索してみても日本語では全然ひっかからないし、
* Icarus では実装されていないし、
* 使い道が思いつかないし、

ということで、timescale

  `timescale 1ps/1ps
  
  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule

ログに、
  #    Time: 4 ps  Iteration: 0  Instance: /testbench
と出るだけの効果だけだっけ？？？

!2006-06-27 Tue

stop

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $stop;
    end
  
    initial begin
      $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00
  ** VVP Stop(0) **
  ** Current simulation time is 4 ticks.
  > ** Continue **
                     4 a=ff b=ff  sum=fe

!2006-06-26 Mon

readmemb

  `define N 4
  
  module testbench;
    reg  [7:0]  a, b;
    wire [7:0]  x;
    reg         CLK, RESET;
    reg  [15:0] data[0:256];
    integer cnt;
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
      $readmemb("2006062600.txt", data);
  
      CLK <= 1; RESET <= 1; a <= 0; b <= 0;
    end
  
    always @(posedge CLK) begin
      if (RESET) begin
        cnt <= 0; RESET <= 0;
      end else if (cnt < `N) begin
        {a, b} <= data[cnt];
        cnt    <= cnt + 1;
      end else
        $finish;
    end
  
    always #(STEP/2) CLK = ~CLK;
  
    initial $monitor($stime, " cnt=%d  a=%h b=%h  sum=%h", cnt, a, b, x);
  
  endmodule

2006062600.txt は、
  00000000_00000000
  00000001_00000101
  10000000_00000001
  11111111_00000001

!2006-06-25 Sun

readmemh

  `define N 4
  
  module testbench;
    reg  [7:0]  a, b;
    wire [7:0]  x;
    reg         CLK, RESET;
    reg  [15:0] data[0:256];
    integer cnt;
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
      $readmemh("2006062500.txt", data);
  
      CLK <= 1; RESET <= 1; a <= 0; b <= 0;
    end
  
    always @(posedge CLK) begin
      if (RESET) begin
        cnt <= 0; RESET <= 0;
      end else if (cnt < `N) begin
        {a, b} <= data[cnt];
        cnt    <= cnt + 1;
      end else
        $finish;
    end
  
    always #(STEP/2) CLK = ~CLK;
  
    initial $monitor($stime, " cnt=%d  a=%h b=%h  sum=%h", cnt, a, b, x);
  
  endmodule

2006062500.txt は、
  00_00
  01_05
  80_01
  ff_01

!2006-06-24 Sat

printtimescale。Icarus verilog 0.8 だと、コンパイルはできるが、実行時エラー

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $printtimescale(itop);
  
      $monitor(" %t %t  a=%h b=%h  sum=%h",
               $stime, $time, a, b, x);
    end
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
  # Time scale of (testbench.itop) is  1ns /  1ns
  #                     0                    0  a=00 b=00  sum=00
  #                     1                    1  a=01 b=05  sum=06
  #                     2                    2  a=80 b=01  sum=81
  #                     3                    3  a=ff b=01  sum=00

!2006-06-23 Fri

timeformat

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial begin
      $timeformat(-9, 3, "ns", 12);
  
      $monitor(" %t %t  a=%h b=%h  sum=%h",
               $stime, $time, a, b, x);
    end
  
  endmodule
で、
        0.000ns      0.000ns  a=00 b=00  sum=00
   1000000000.000ns 1000000000.000ns  a=01 b=05  sum=06
   2000000000.000ns 2000000000.000ns  a=80 b=01  sum=81
   3000000000.000ns 3000000000.000ns  a=ff b=01  sum=00

!2006-06-22 Thu

realtime

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($realtime, "  a=%h b=%h  sum=%h",
                     a, b, x);
  
  endmodule
で、
  0  a=00 b=00  sum=00
  1  a=01 b=05  sum=06
  2  a=80 b=01  sum=81
  3  a=ff b=01  sum=00

どこが real ？

!2006-06-21 Wed

stime と time。

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor(" %t %t  a=%h b=%h  sum=%h",
                     $stime, $time, a, b, x);
  
  endmodule
で、
                      0                    0  a=00 b=00  sum=00
                      1                    1  a=01 b=05  sum=06
                      2                    2  a=80 b=01  sum=81
                      3                    3  a=ff b=01  sum=00

違いある？
昔、Verilog XL 使ったときは違いあったような気がしたのだが…

!2006-06-20 Tue

fstrobe

  `define TEXT_FILE "2006062000.txt"
  
  module testbench;
    reg        clk;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 10;
    integer fd;
  
    assign x = a + b;
  
    initial begin
      fd = $fopen(`TEXT_FILE);
  
            clk <= 1;
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
  
      $fclose(fd);
      $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always #(STEP/2) begin
      $fstrobe(fd, $stime, " clk=%b a=%h b=%h  sum=%h", clk, a, b, x);
    end
  
  endmodule

!2006-06-19 Mon

fwrite

  `define TEXT_FILE "2006061900.txt"
  
  module testbench;
    reg        clk;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 10;
    integer fd;
  
    assign x = a + b;
  
    initial begin
      fd = $fopen(`TEXT_FILE);
  
            clk <= 1;
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
  
      $fclose(fd);
      $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always #(STEP/2) begin
      $fwrite(fd, $stime, " clk=%b a=%h b=%h  sum=%h\n", clk, a, b, x);
    end
  
  endmodule

!2006-06-18 Sun

fdisplay

  `define TEXT_FILE "2006061800.txt"
  
  module testbench;
    reg        clk;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 10;
    integer fd;
  
    assign x = a + b;
  
    initial begin
      fd = $fopen(`TEXT_FILE);
  
            clk <= 1;
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
  
      $fclose(fd);
      $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always #(STEP/2) begin
      $fdisplay(fd, $stime, " clk=%b a=%h b=%h  sum=%h", clk, a, b, x);
    end
  
  endmodule

!2006-06-17 Sat

fmonitor

  `define TEXT_FILE "2006061700.txt"
  
  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
    integer fd;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
  
      $fclose(fd);
      $finish;
    end
  
    initial begin
      fd = $fopen(`TEXT_FILE);
  
      $fmonitor(fd, $stime, " a=%h b=%h  sum=%h", a, b, x);
    end
  
  endmodule

Icarus verilog 0.8 だと、コンパイルはできるが、実行時、以下のエラー
  $fmonitor: This task not defined by any modules. I cannot compile it.

modelsim では、実行できたので、記述が間違いという訳でもなさそうなのだが…。

!2006-06-16 Fri

strobe

違いの分かる例 作れず…。
と、思っていたら、display とはタイミングが違っていた。
monitor と同じような感じ？？？

  module testbench;
    reg        clk;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            clk <= 1;
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always #(STEP/2) $strobe($stime, " clk=%b a=%h b=%h  sum=%h", clk, a, b, x);
  
  endmodule
で、
                     5 clk=0 a=00 b=00  sum=00
                    10 clk=1 a=01 b=05  sum=06
                    15 clk=0 a=01 b=05  sum=06
                    20 clk=1 a=80 b=01  sum=81
                    25 clk=0 a=80 b=01  sum=81
                    30 clk=1 a=ff b=01  sum=00
                    35 clk=0 a=ff b=01  sum=00

!2006-06-15 Thu

write。改行がないだけの違い

  module testbench;
    reg        clk;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            clk <= 1;
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always #(STEP/2) $write($stime, " clk=%b a=%h b=%h  sum=%h\n", clk, a, b, x);
  
  endmodule
で、
                     5 clk=0 a=00 b=00  sum=00
                    10 clk=1 a=00 b=00  sum=00
                    15 clk=0 a=01 b=05  sum=06
                    20 clk=1 a=01 b=05  sum=06
                    25 clk=0 a=80 b=01  sum=81
                    30 clk=1 a=80 b=01  sum=81
                    35 clk=0 a=ff b=01  sum=00

!2006-06-14 Wed

display

  module testbench;
    reg        clk;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 10;
  
    assign x = a + b;
  
    initial begin
            clk <= 1;
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always #(STEP/2) $display($stime, " clk=%b a=%h b=%h  sum=%h", clk, a, b, x);
  
  endmodule
で、
                     5 clk=0 a=00 b=00  sum=00
                    10 clk=1 a=00 b=00  sum=00
                    15 clk=0 a=01 b=05  sum=06
                    20 clk=1 a=01 b=05  sum=06
                    25 clk=0 a=80 b=01  sum=81
                    30 clk=1 a=80 b=01  sum=81
                    35 clk=0 a=ff b=01  sum=00

!2006-06-13 Tue

monitor (display)書式

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor("%t a=%h b=%h  sum=%h %s %e %f",
                     $stime, a, b, x, "foo", 1.2, 1.2);
  
  endmodule
で、
                     0 a=00 b=00  sum=00 foo 1.2 1.200000
                     1 a=01 b=05  sum=06 foo 1.2 1.200000
                     2 a=80 b=01  sum=81 foo 1.2 1.200000
                     3 a=ff b=01  sum=00 foo 1.2 1.200000

time は %d でも一応実行できたが、どれでも動くかは不明

!2006-06-12 Mon

monitor (display)書式

  module testbench;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a + b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%b %o %d %h",
                     a, b, x, x, x, x);
  
  endmodule
で、
                     0 a=00 b=00  sum=00000000 000   0 00
                     1 a=01 b=05  sum=00000110 006   6 06
                     2 a=80 b=01  sum=10000001 201 129 81
                     3 a=ff b=01  sum=00000000 000   0 00

なぜ、先頭に $stime を書いても良いのかは分からず書いていたり。
文法的にはどうなっているんだ？

!2006-06-11 Sun

ユーザ定義プリミティブ

  module testbench;
    reg  a;
    wire x;
  
    parameter STEP = 1;
  
    my_not inot(x, a);
  
    initial begin
            a <= 0;
      #STEP a <= 1;
      #STEP a <= 0;
      $finish;
    end
  
    initial $monitor($stime, " a=%h not=%h", a, x);
  
  endmodule
  
  primitive my_not(out, in);
    input  in;
    output out;
  
    table
      // in : out
          0 : 1;
          1 : 0;
    endtable
  
  endprimitive
で、
                     0 a=0 not=1
                     1 a=1 not=0

!2006-06-10 Sat

まだまだ、プリミティブゲート

  module testbench;
    reg  a;
    wire x1, x2;
  
    parameter STEP = 1;
  
    buf ibuf(x1, a);
    not inot(x2, a);
  
    initial begin
            a <= 0;
      #STEP a <= 1;
      #STEP a <= 0;
      $finish;
    end
  
    initial $monitor($stime, " a=%h buf=%h not=%h", a, x1, x2);
  
  endmodule
で、
                     0 a=0 buf=0 not=1
                     1 a=1 buf=1 not=0

!2006-06-09 Fri

まだまだ、プリミティブゲート

  module testbench;
    reg  a, b;
    wire x1, x2, x3, x4, x5, x6;
  
    parameter STEP = 1;
  
     and  iand(x1, a, b);
    nand inand(x2, a, b);
      or   ior(x3, a, b);
     nor  inor(x4, a, b);
     xor  ixor(x5, a, b);
    xnor ixnor(x6, a, b);
  
    initial begin
            a <= 0; b <= 0;
      #STEP a <= 0; b <= 1;
      #STEP a <= 1; b <= 0;
      #STEP a <= 1; b <= 1;
      #STEP a <= 0; b <= 1;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  and=%h nand=%h or=%h nor=%h xor=%h xnor=%h", a, b, x1, x2, x3, x4, x5, x6);
  
  endmodule
で、
                     0 a=0 b=0  and=0 nand=1 or=0 nor=1 xor=0 xnor=1
                     1 a=0 b=1  and=0 nand=1 or=1 nor=0 xor=1 xnor=0
                     2 a=1 b=0  and=0 nand=1 or=1 nor=0 xor=1 xnor=0
                     3 a=1 b=1  and=1 nand=0 or=1 nor=0 xor=0 xnor=1

!2006-06-08 Thu

プリミティブゲート。遅延を与えることができるらしい

  module testbench;
    reg  a, b;
    wire x;
  
    parameter STEP = 10;
  
    and #(1,2) iand(x, a, b);
  
    initial begin
            a <= 0; b <= 0;
      #STEP a <= 0; b <= 1;
      #STEP a <= 1; b <= 0;
      #STEP a <= 1; b <= 1;
      #STEP a <= 0; b <= 1;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  out=%h", a, b, x);
  
  endmodule
で、
                     0 a=0 b=0  out=x
                     2 a=0 b=0  out=0
                    10 a=0 b=1  out=0
                    20 a=1 b=0  out=0
                    21 a=1 b=0  out=0
                    22 a=1 b=0  out=0
                    30 a=1 b=1  out=0
                    31 a=1 b=1  out=1

遅延値をひとつにすると、
  module testbench;
    reg  a, b;
    wire x;
  
    parameter STEP = 10;
  
    and #(1) iand(x, a, b);
  
    initial begin
            a <= 0; b <= 0;
      #STEP a <= 0; b <= 1;
      #STEP a <= 1; b <= 0;
      #STEP a <= 1; b <= 1;
      #STEP a <= 0; b <= 1;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  out=%h", a, b, x);
  
  endmodule
で、
                     0 a=0 b=0  out=x
                     1 a=0 b=0  out=0
                    10 a=0 b=1  out=0
                    20 a=1 b=0  out=0
                    21 a=1 b=0  out=0
                    30 a=1 b=1  out=0
                    31 a=1 b=1  out=1

!2006-06-07 Wed

プリミティブゲート。2入力に限定されない

  module testbench;
    reg  a, b, c;
    wire x;
  
    parameter STEP = 1;
  
    and iand(x, a, b, c);
  
    initial begin
            a <= 0; b <= 0; c <= 0;
      #STEP a <= 0; b <= 1; c <= 1;
      #STEP a <= 1; b <= 0; c <= 0;
      #STEP a <= 1; b <= 1; c <= 1;
      #STEP a <= 0; b <= 1; c <= 0;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h c=%h  out=%h", a, b, c, x);
  
  endmodule
で、
                     0 a=0 b=0 c=0  out=0
                     1 a=0 b=1 c=1  out=0
                     2 a=1 b=0 c=0  out=0
                     3 a=1 b=1 c=1  out=1

!2006-06-06 Tue

プリミティブゲート

  module testbench;
    reg  a, b;
    wire x;
  
    parameter STEP = 1;
  
    and iand(x, a, b);
  
    initial begin
            a <= 0; b <= 0;
      #STEP a <= 0; b <= 1;
      #STEP a <= 1; b <= 0;
      #STEP a <= 1; b <= 1;
      #STEP a <= 0; b <= 1;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  out=%h", a, b, x);
  
  endmodule
で、
                     0 a=0 b=0  out=0
                     1 a=0 b=1  out=0
                     2 a=1 b=0  out=0
                     3 a=1 b=1  out=1

「and iand(x, a, b);」は、「and(x, a, b);」でも良い

!2006-06-05 Mon

defparam。これは初耳。

インスタンス化の後に書いても大丈夫みたい。

  module testbench;
    reg  [15:0] a, b;
    wire [15:0] x;
  
    parameter STEP = 1;
  
    defparam i16sum.width = 16;
    sum i16sum(a, b, x);
  
    initial begin
            a <= 0;        b <= 0;
      #STEP a <= 1;        b <= 5;
      #STEP a <= 16'h8000; b <= 1;
      #STEP a <= 16'hffff; b <= 1;
      #STEP a <= 16'hffff; b <= 16'hffff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module sum(a, b, x);
    parameter width = 8;
    input  [width-1:0] a;
    input  [width-1:0] b;
    output [width-1:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=0000 b=0000  sum=0000
                     1 a=0001 b=0005  sum=0006
                     2 a=8000 b=0001  sum=8001
                     3 a=ffff b=0001  sum=0000

!2006-06-04 Sun

パラメータ、複数。

  module testbench;
    reg  [7:0]  a1, b1;
    reg  [15:0] a2, b2;
    wire [7:0]  x1;
    wire [15:0] x2;
  
    parameter STEP = 1;
  
    sum #(8,16) isum(a1, b1, x1, a2, b2, x2);
  
    initial begin
            a1 <= 0;     b1 <= 0;     a2 <= 0;        b2 <= 0;
      #STEP a1 <= 1;     b1 <= 5;     a2 <= 1;        b2 <= 5;
      #STEP a1 <= 8'h80; b1 <= 1;     a2 <= 16'h8000; b2 <= 1;
      #STEP a1 <= 8'hff; b1 <= 1;     a2 <= 16'hffff; b2 <= 1;
      #STEP a1 <= 8'hff; b1 <= 8'hff; a2 <= 16'hffff; b2 <= 16'hffff;
      $finish;
    end
  
    initial $monitor($stime, " a1=%h b1=%h a2=%h b2=%h  sum1=%h sum2=%h",
                     a1, b1, a2, b2, x1, x2);
  
  endmodule
  
  module sum(a1, b1, x1, a2, b2, x2);
    parameter width1 = 8;
    parameter width2 = 16;
    input  [width1-1:0] a1, b1;
    input  [width2-1:0] a2, b2;
    output [width1-1:0] x1;
    output [width2-1:0] x2;
  
    assign x1 = a1 + b1;
    assign x2 = a2 + b2;
  
  endmodule
で、
                     0 a1=00 b1=00 a2=0000 b2=0000  sum1=00 sum2=0000
                     1 a1=01 b1=05 a2=0001 b2=0005  sum1=06 sum2=0006
                     2 a1=80 b1=01 a2=8000 b2=0001  sum1=81 sum2=8001
                     3 a1=ff b1=01 a2=ffff b2=0001  sum1=00 sum2=0000

!2006-06-03 Sat

パラメータ

  module testbench;
    reg  [7:0]  a1, b1, a2, b2;
    reg  [15:0] a3, b3;
    wire [7:0]  x1, x2;
    wire [15:0] x3;
  
    parameter STEP = 1;
  
    sum       isum(a1, b1, x1);
    sum #(8)  i08sum(a2, b2, x2);
    sum #(16) i16sum(a3, b3, x3);
  
    initial begin
            a1 <= 0;     b1 <= 0;     a2 <= 0;     b2 <= 0;     a3 <= 0;        b3 <= 0;
      #STEP a1 <= 1;     b1 <= 5;     a2 <= 1;     b2 <= 5;     a3 <= 1;        b3 <= 5;
      #STEP a1 <= 8'h80; b1 <= 1;     a2 <= 8'h80; b2 <= 1;     a3 <= 16'h8000; b3 <= 1;
      #STEP a1 <= 8'hff; b1 <= 1;     a2 <= 8'hff; b2 <= 1;     a3 <= 16'hffff; b3 <= 1;
      #STEP a1 <= 8'hff; b1 <= 8'hff; a2 <= 8'hff; b2 <= 8'hff; a3 <= 16'hffff; b3 <= 16'hffff;
      $finish;
    end
  
    initial $monitor($stime, " a1=%h b1=%h a2=%h b2=%h a3=%h b3=%h  sum1=%h sum2=%h sum3=%h",
                     a1, b1, a2, b2, a3, b3, x1, x2, x3);
  
  endmodule
  
  module sum(a, b, x);
    parameter width = 8;
    input  [width-1:0] a;
    input  [width-1:0] b;
    output [width-1:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a1=00 b1=00 a2=00 b2=00 a3=0000 b3=0000  sum1=00 sum2=00 sum3=0000
                     1 a1=01 b1=05 a2=01 b2=05 a3=0001 b3=0005  sum1=06 sum2=06 sum3=0006
                     2 a1=80 b1=01 a2=80 b2=01 a3=8000 b3=0001  sum1=81 sum2=81 sum3=8001
                     3 a1=ff b1=01 a2=ff b2=01 a3=ffff b3=0001  sum1=00 sum2=00 sum3=0000

「#(8)」は、「#8」でも良いのかな(複数パラメターがない場合は)？

!2006-06-02 Fri

インスタンス化。並べて書けるんだ〜

  module testbench;
    reg  [7:0]  a1, b1, a2, b2;
    wire [7:0]  x1, x2;
  
    parameter STEP = 1;
  
    sum isum1(a1, b1, x1), isum2(a2, b2, x2);
  
    initial begin
            a1 <= 0;     b1 <= 0;     a2 <= 0;     b2 <= 0;
      #STEP a1 <= 1;     b1 <= 5;     a2 <= 1;     b2 <= 5;
      #STEP a1 <= 8'h80; b1 <= 1;     a2 <= 8'h80; b2 <= 1;
      #STEP a1 <= 8'hff; b1 <= 1;     a2 <= 8'hff; b2 <= 1;
      #STEP a1 <= 8'hff; b1 <= 8'hff; a2 <= 8'hff; b2 <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a1=%h b1=%h a2=%h b2=%h  sum1=%h sum2=%h",
                     a1, b1, a2, b2, x1, x2);
  
  endmodule
  
  module sum(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a1=00 b1=00 a2=00 b2=00  sum1=00 sum2=00
                     1 a1=01 b1=05 a2=01 b2=05  sum1=06 sum2=06
                     2 a1=80 b1=01 a2=80 b2=01  sum1=81 sum2=81
                     3 a1=ff b1=01 a2=ff b2=01  sum1=00 sum2=00

!2006-06-01 Thu

テーマなんだったっけ？

  module testbench;
    reg        clk;
    reg  [7:0] x;
    wire [7:0] y;
  
    parameter STEP = 10;
  
    top itop(clk, x, y);
  
    initial begin
            clk <= 1;
            x <= 0;
      #STEP x <= 1;
      #STEP x <= 2;
      #STEP x <= 3;
      #STEP x <= 4;
      #STEP x <= 5;
      #STEP x <= 6;
      #STEP x <= 7;
      #STEP x <= 8;
      #STEP
      $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    initial $monitor($stime, " clk=%b x=%h  y=%h", clk, x, y);
  
  endmodule
  
  module top(clk, x, y);
    input        clk;
    input  [7:0] x;
    output [7:0] y;
  
    assign y = fun(x);
  
    function [7:0] fun;
      input  [7:0] x;
  
      integer i;
  
      begin
        fun = 0;
  
        for (i = 0; i < 8; i = i + 1)
          if (x[i] == 1)
            fun = i;
      end
  
    endfunction
  
  endmodule
で、
                     0 clk=1 x=00  y=00
                     5 clk=0 x=00  y=00
                    10 clk=1 x=01  y=00
                    15 clk=0 x=01  y=00
                    20 clk=1 x=02  y=01
                    25 clk=0 x=02  y=01
                    30 clk=1 x=03  y=01
                    35 clk=0 x=03  y=01
                    40 clk=1 x=04  y=02
                    45 clk=0 x=04  y=02
                    50 clk=1 x=05  y=02
                    55 clk=0 x=05  y=02
                    60 clk=1 x=06  y=02
                    65 clk=0 x=06  y=02
                    70 clk=1 x=07  y=02
                    75 clk=0 x=07  y=02
                    80 clk=1 x=08  y=03
                    85 clk=0 x=08  y=03

!2006-05-31 Wed

遅延式

  module testbench;
    reg        clk;
    reg  [7:0] x1, x2, x3;
  
    parameter STEP = 10;
  
    initial begin
            x1 <= 0; x2 <= 0; x3 <= 0; clk <= 1;
      #STEP x1 <= 1;
      #STEP x1 <= 2;
      #STEP x1 <= 3;
      #STEP $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always @(posedge clk)
      #1 x2 = x1;
  
    always @(posedge clk)
      #1 x3 = x2;
  
    initial $monitor($stime, " clk=%b x1=%h x2=%h x3=%h", clk, x1, x2, x3);
  
  endmodule
で、
                     0 clk=1 x1=00 x2=00 x3=00
                     5 clk=0 x1=00 x2=00 x3=00
                    10 clk=1 x1=01 x2=00 x3=00
                    11 clk=1 x1=01 x2=01 x3=01
                    15 clk=0 x1=01 x2=01 x3=01
                    20 clk=1 x1=02 x2=01 x3=01
                    21 clk=1 x1=02 x2=02 x3=01
                    25 clk=0 x1=02 x2=02 x3=01
                    30 clk=1 x1=03 x2=02 x3=01
                    31 clk=1 x1=03 x2=03 x3=03
                    35 clk=0 x1=03 x2=03 x3=03

場所を変えて、
  module testbench;
    reg        clk;
    reg  [7:0] x1, x2, x3;
  
    parameter STEP = 10;
  
    initial begin
            x1 <= 0; x2 <= 0; x3 <= 0; clk <= 1;
      #STEP x1 <= 1;
      #STEP x1 <= 2;
      #STEP x1 <= 3;
      #STEP $finish;
    end
  
    always #(STEP/2) clk = ~clk;
  
    always @(posedge clk)
      x2 = #1 x1;
  
    always @(posedge clk)
      x3 = #1 x2;
  
    initial $monitor($stime, " clk=%b x1=%h x2=%h x3=%h", clk, x1, x2, x3);
  
  endmodule
で、
                     0 clk=1 x1=00 x2=00 x3=00
                     5 clk=0 x1=00 x2=00 x3=00
                    10 clk=1 x1=01 x2=00 x3=00
                    15 clk=0 x1=01 x2=00 x3=00
                    20 clk=1 x1=02 x2=00 x3=00
                    21 clk=1 x1=02 x2=01 x3=00
                    25 clk=0 x1=02 x2=01 x3=00
                    30 clk=1 x1=03 x2=01 x3=00
                    31 clk=1 x1=03 x2=02 x3=01
                    35 clk=0 x1=03 x2=02 x3=01

ふーむ、良くわからん

!2006-05-30 Tue

遅延式。意味が分からないが、reg も書けるようだ。

  module testbench;
    reg  [7:0] x;
  
    parameter STEP = 10;
  
    initial begin
                x <= 0;
      #STEP     x <= 1;
      #STEP     x <= 2;
      #x        x <= 3;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                    10 x=01
                    20 x=02
                    21 x=03

結果は、良く分からないなあ〜

!2006-05-29 Mon

遅延式。結構なんでも書けるっぽい

  module testbench;
    reg  [7:0] x;
  
    parameter STEP = 10;
  
    initial begin
                x <= 0;
      #STEP     x <= 1;
      #STEP     x <= 2;
      #(STEP+1) x <= 3;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                    10 x=01
                    20 x=02
                    31 x=03

!2006-05-28 Sun

遅延式

  module testbench;
    reg  [7:0] x;
  
    parameter STEP = 10;
  
    initial begin
            x <=    0;
      #STEP x <= #1 1;
      #STEP x <=    2;
      #STEP x <=    3;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                    11 x=01
                    20 x=02
                    30 x=03

!2006-05-27 Sat

forever

  module testbench;
    reg clk;
  
    parameter STEP = 10;
  
    initial begin
      clk <= 0;
  
      forever #(STEP/2) clk = ~clk;
    end
  
    initial begin
      #30 ;
      $finish;
    end
  
    initial $monitor($stime, " clk=%d", clk);
  
  endmodule
で、
                     0 clk=0
                     5 clk=1
                    10 clk=0
                    15 clk=1
                    20 clk=0
                    25 clk=1

別に、always で良さそうだが

  module testbench;
    reg clk;
  
    parameter STEP = 10;
  
    initial begin
      clk <= 0;
    end
  
    always #(STEP/2) clk = ~clk;
  
    initial begin
      #30 ;
      $finish;
    end
  
    initial $monitor($stime, " clk=%d", clk);
  
  endmodule
で、
                     0 clk=0
                     5 clk=1
                    10 clk=0
                    15 clk=1
                    20 clk=0
                    25 clk=1

!2006-05-26 Fri

forever

  module testbench;
  
    parameter STEP = 1;
  
    initial begin
      forever begin
        #STEP ;
      end
    end
  
    initial begin
      #10 ;
      $finish;
    end
  
    initial $monitor($stime);
  
  endmodule
で、
                     0
うむ。じゃ、これは？

  module testbench;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin
      x <= 0;
      forever begin
        #STEP x <= x + 1;
      end
    end
  
    initial begin
      #3 ;
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                     1 x=01
                     2 x=02

!2006-05-25 Thu

repeat

  module testbench;
    reg  [7:0] x;
    wire [7:0] y;
  
    parameter STEP = 1;
  
    assign y = fun(x);
  
    initial begin
            x <= 0;
      #STEP x <= 1;
      #STEP x <= 2;
      #STEP x <= 3;
      #STEP x <= 4;
      #STEP x <= 5;
      #STEP x <= 6;
      #STEP x <= 7;
      #STEP x <= 8;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h  y=%h", x, y);
  
    function [7:0] fun;
      input  [7:0] x;
  
      integer i;
  
      begin
        fun = 0;
  
        i = 0;
        repeat (8) begin
          if (x[i] == 1)
            fun = i;
          i = i + 1;
        end
      end
  
    endfunction
  
  endmodule
で、
                     0 x=00  y=00
                     1 x=01  y=00
                     2 x=02  y=01
                     3 x=03  y=01
                     4 x=04  y=02
                     5 x=05  y=02
                     6 x=06  y=02
                     7 x=07  y=02
                     8 x=08  y=03

!2006-05-24 Wed

また while。for のを書き直しただけ。

  module testbench;
    reg  [7:0] x;
    wire [7:0] y;
  
    parameter STEP = 1;
  
    assign y = fun(x);
  
    initial begin
            x <= 0;
      #STEP x <= 1;
      #STEP x <= 2;
      #STEP x <= 3;
      #STEP x <= 4;
      #STEP x <= 5;
      #STEP x <= 6;
      #STEP x <= 7;
      #STEP x <= 8;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h  y=%h", x, y);
  
    function [7:0] fun;
      input  [7:0] x;
  
      integer i;
  
      begin
        fun = 0;
  
        i = 0;
        while (i < 8) begin
          if (x[i] == 1)
            fun = i;
          i = i + 1;
        end
      end
  
    endfunction
  
  endmodule
で、
                     0 x=00  y=00
                     1 x=01  y=00
                     2 x=02  y=01
                     3 x=03  y=01
                     4 x=04  y=02
                     5 x=05  y=02
                     6 x=06  y=02
                     7 x=07  y=02
                     8 x=08  y=03

!2006-05-23 Tue

while

  module testbench;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin
            x <= 8'h00;
      while (x < 3) begin
        #STEP x = x + 1;
      end
      #STEP x <= 8'h00;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00

うむ？for と while は、ほぼ同じものだと思ったのに。

「<=」を「=」に変更。

  module testbench;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin
      x = 8'h00;
  
      while (x < 3) begin
        #STEP x = x + 1;
      end
      #STEP x <= 8'h00;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                     1 x=01
                     2 x=02
                     3 x=03
                     4 x=00

!2006-05-22 Mon

またまた for。
回路という意味では、function 内とかで使うのが普通なのだろうか？
(実際は testbench 中に書いちゃっているけど)

  module testbench;
    reg  [7:0] x;
    wire [7:0] y;
  
    parameter STEP = 1;
  
    assign y = fun(x);
  
    initial begin
            x <= 0;
      #STEP x <= 1;
      #STEP x <= 2;
      #STEP x <= 3;
      #STEP x <= 4;
      #STEP x <= 5;
      #STEP x <= 6;
      #STEP x <= 7;
      #STEP x <= 8;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h  y=%h", x, y);
  
    function [7:0] fun;
      input  [7:0] x;
  
      integer i;
  
      for (i = 0; i < 8; i = i + 1)
        if (x[i] == 1)
          fun = i;
  
    endfunction
  
  endmodule
で、
                     0 x=00  y=xx
                     1 x=01  y=00
                     2 x=02  y=01
                     3 x=03  y=01
                     4 x=04  y=02
                     5 x=05  y=02
                     6 x=06  y=02
                     7 x=07  y=02
                     8 x=08  y=03

!2006-05-21 Sun

また、for

for の要素には、遅延要素が書けないのかなと思ったが、書けるようだ。

* for の中に #STEP のみだとエラー
* #STEP だけでなく ; を書くと OK

  module testbench;
    reg  [7:0] x, y;
  
    parameter STEP = 1;
  
    initial begin
            x <= 8'h00; y <= 8'h00;
      for (x = 0; x < 3; x = x + 1) begin
        #STEP y <= x;
      end
      #STEP x <= 8'h00;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h  y=%h", x, y);
  
  endmodule
で、
                     0 x=00  y=00
                     1 x=01  y=00
                     2 x=02  y=01
                     3 x=03  y=02
                     4 x=00  y=02

!2006-05-20 Sat

for

  module testbench;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin
            x <= 8'h00;
      for (x = 0; x < 8'hff; x = x + 1) begin
      end
      #STEP x <= 8'h55;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                     1 x=55

うーむ、無意味じゃ

!2006-05-19 Fri

casez

  module testbench;
    reg  [7:0] a, b;
    reg  [7:0] f;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    add_sub ias(a, b, f, x);
  
    initial begin
            a <= 1;     b <= 2; f <= 8'hz0;
      #STEP                     f <= 8'hf0;
      #STEP                     f <= 8'h00;
      #STEP                     f <= 8'hff;
      #STEP a <= 8'h80; b <= 1; f <= 8'h01;
      #STEP                     f <= 8'hz1;
      #STEP                     f <= 8'hf1;
      #STEP                     f <= 8'hff;
      #STEP a <= 8'h02; b <= 3; f <= 8'h02;
      #STEP                     f <= 8'hzf;
      #STEP                     f <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h f=%h  x=%h", a, b, f, x);
  
  endmodule
  
  module add_sub(a, b, f, x);
    input  [7:0] a;
    input  [7:0] b;
    input  [7:0] f;
    output [7:0] x;
    reg    [7:0] reg_x;
  
    assign x = reg_x;
  
    always @(a or b or f) begin
      casez (f)
        8'hz0:   reg_x <= a + b;
        8'hz1:   reg_x <= a - b;
        default: reg_x <= a * b;
      endcase
    end
  
  endmodule
で、
                     0 a=01 b=02 f=z0  x=03
                     1 a=01 b=02 f=f0  x=03
                     2 a=01 b=02 f=00  x=03
                     3 a=01 b=02 f=ff  x=02
                     4 a=80 b=01 f=01  x=7f
                     5 a=80 b=01 f=z1  x=7f
                     6 a=80 b=01 f=f1  x=7f
                     7 a=80 b=01 f=ff  x=80
                     8 a=02 b=03 f=02  x=06
                     9 a=02 b=03 f=zf  x=06
                    10 a=02 b=03 f=ff  x=06

!2006-05-18 Thu

casex

  module testbench;
    reg  [7:0] a, b;
    reg  [7:0] f;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    add_sub ias(a, b, f, x);
  
    initial begin
            a <= 1;     b <= 2; f <= 8'hx0;
      #STEP                     f <= 8'hf0;
      #STEP                     f <= 8'h00;
      #STEP                     f <= 8'hff;
      #STEP a <= 8'h80; b <= 1; f <= 8'h01;
      #STEP                     f <= 8'hx1;
      #STEP                     f <= 8'hf1;
      #STEP                     f <= 8'hff;
      #STEP a <= 8'h02; b <= 3; f <= 8'h02;
      #STEP                     f <= 8'hxf;
      #STEP                     f <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h f=%h  x=%h", a, b, f, x);
  
  endmodule
  
  module add_sub(a, b, f, x);
    input  [7:0] a;
    input  [7:0] b;
    input  [7:0] f;
    output [7:0] x;
    reg    [7:0] reg_x;
  
    assign x = reg_x;
  
    always @(a or b or f) begin
      casex (f)
        8'hx0:   reg_x <= a + b;
        8'hx1:   reg_x <= a - b;
        default: reg_x <= a * b;
      endcase
    end
  
  endmodule
で、
                     0 a=01 b=02 f=x0  x=03
                     1 a=01 b=02 f=f0  x=03
                     2 a=01 b=02 f=00  x=03
                     3 a=01 b=02 f=ff  x=02
                     4 a=80 b=01 f=01  x=7f
                     5 a=80 b=01 f=x1  x=7f
                     6 a=80 b=01 f=f1  x=7f
                     7 a=80 b=01 f=ff  x=80
                     8 a=02 b=03 f=02  x=06
                     9 a=02 b=03 f=xf  x=06
                    10 a=02 b=03 f=ff  x=06

!2006-05-17 Wed

続 case

  module testbench;
    reg  [7:0] a, b;
    reg  [1:0] f;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    add_sub ias(a, b, f, x);
  
    initial begin
            a <= 1;     b <= 2; f <= 0;
      #STEP a <= 2;     b <= 5;
      #STEP a <= 8'h80; b <= 1; f <= 1;
      #STEP a <= 8'h02; b <= 3; f <= 2;
      #STEP a <= 8'h02; b <= 3;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h f=%h  x=%h", a, b, f, x);
  
  endmodule
  
  module add_sub(a, b, f, x);
    input  [7:0] a;
    input  [7:0] b;
    input  [1:0] f;
    output [7:0] x;
    reg    [7:0] reg_x;
  
    assign x = reg_x;
  
    always @(a or b or f) begin
      case (f)
        0:       reg_x <= a + b;
        1:       reg_x <= a - b;
        default: reg_x <= a * b;
      endcase
    end
  
  endmodule
で、
                     0 a=01 b=02 f=0  x=03
                     1 a=02 b=05 f=0  x=07
                     2 a=80 b=01 f=1  x=7f
                     3 a=02 b=03 f=2  x=06

!2006-05-16 Tue

case

  module testbench;
    reg  [7:0] x, y;
  
    parameter STEP = 1;
  
    initial begin
            x <= 8'h01;
            y <= 8'h00;
      #STEP
        case (x)
          0:       y <= 8'hff;
          1:       y <= 8'hfe;
          default: y <= 8'h55;
        endcase
      #STEP x <= 8'hff;
      #STEP x <= 8'h00;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h y=%h", x, y);
  
  endmodule
で、
                     0 x=01 y=00
                     1 x=01 y=fe
                     2 x=ff y=fe
                     3 x=00 y=fe

!2006-05-15 Mon

  module testbench;
    reg  [7:0] a, b;
    reg        f;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    add_sub ias(a, b, f, x);
  
    initial begin
            a <= 0;     b <= 0; f <= 1;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1; f <= 0;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h f=%b  sum=%h", a, b, f, x);
  
  endmodule
  
  module add_sub(a, b, f, x);
    input  [7:0] a;
    input  [7:0] b;
    input        f;
    output [7:0] x;
    wire   [7:0] add, sub;
  
    assign x = f ? add : sub;
    assign add = a + b;
    assign sub = a - b;
  
  endmodule
で、
                     0 a=00 b=00 f=1  sum=00
                     1 a=01 b=05 f=1  sum=06
                     2 a=80 b=01 f=0  sum=7f
                     4 a=ff b=01 f=0  sum=fe

こういう切り替えだと if の入り込む余地がないか？？？

!2006-05-14 Sun

また、if

  module testbench;
    reg  [7:0] a, b;
    reg        f;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    add_sub ias(a, b, f, x);
  
    initial begin
            a <= 0;     b <= 0; f <= 1;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1; f <= 0;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h f=%b  sum=%h", a, b, f, x);
  
  endmodule
  
  module add_sub(a, b, f, x);
    input  [7:0] a;
    input  [7:0] b;
    input        f;
    output [7:0] x;
    reg    [7:0] reg_x;
  
    assign x = reg_x;
  
    always @(a or b or f) begin
      if (f)
        reg_x <= a + b;
      else
        reg_x <= a - b;
    end
  
  endmodule
で、
                     0 a=00 b=00 f=1  sum=00
                     1 a=01 b=05 f=1  sum=06
                     2 a=80 b=01 f=0  sum=7f
                     4 a=ff b=01 f=0  sum=fe

!2006-05-13 Sat

if

  module test_tb;
    reg  [7:0] x, y;
  
    parameter STEP = 1;
  
    initial begin
            x <= 8'h00;
            y <= 8'h00;
      #STEP
        if (x == 0)
          y <= 8'hff;
      #STEP x <= 8'hff;
      #STEP x <= 8'h00;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h y=%h", x, y);
  
  endmodule
で、
                     0 x=00 y=00
                     1 x=00 y=ff
                     2 x=ff y=ff
                     3 x=00 y=ff

これも大丈夫なのか〜

!2006-05-12 Fri

disable

  module test_tb;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin : foo
            x <= 8'h00;
      #STEP x <= 8'h55; disable foo;
      #STEP x <= 8'hff;
      #STEP $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                     1 x=55

  module test_tb;
    reg  clk;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    always #STEP clk = ~clk;
  
    initial begin : foo
      forever @(clk) begin : bar
        x <= x + 1;
        if (x > 3) begin
          disable foo;
        end
      end
    end
  
    initial begin
      x <= 8'h00;
      clk <= 0;
  
      #10 $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=01
                     1 x=02
                     2 x=03
                     3 x=04
                     4 x=05

!2006-05-11 Thu

fork, join

  module test_tb;
    reg  [7:0] x;
  
    initial fork
          x <= 8'h00;
      #1  x <= 8'h55;
      #2  x <= 8'hff;
      #3  x <= 8'h00;
      #10 $finish;
    join
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=00
                     1 x=55
                     2 x=ff
                     3 x=00

!2006-05-10 Wed

ブロック名。reg をローカル定義

  module test_tb;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin :foo
      reg [7:0] xx;
  
            xx <= 8'h55;
      #STEP x  <= xx;
      #STEP x  <= 8'hff;
      #STEP x  <= 8'h00;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule

!2006-05-09 Tue

ブロック名。こんなものがあったのか。
ローカルな定義には、ブロック名が必要らしい。

  module test_tb;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin :foo
            x <= 8'h00;
      #STEP x <= 8'hff;
      #STEP x <= 8'h00;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule

!2006-05-08 Mon

initial 文

  module test_tb;
    reg  [7:0] x;
  
    parameter STEP = 1;
  
    initial begin
            x <= 8'h00;
      #STEP x <= 8'hff;
      #STEP x <= 8'h00;
      #STEP
      $finish;
    end
  
    initial begin
            x <= 8'hff;
      #STEP x <= 8'h00;
      #STEP x <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=ff
                     1 x=00
                     2 x=ff

こういう記述が認められているのかは不明。

!2006-05-07 Sun

always 文

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
    reg    [7:0] reg_x;
  
    assign x = reg_x;
  
    always @(a or b) begin
      reg_x <= a + b;
    end
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

!2006-05-06 Sat

assign

  module test_tb;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = 8'hff;
  
    initial begin
            
      #STEP
      #STEP
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=ff

!2006-05-05 Fri

宣言時に代入

  module test_tb;
    wire [7:0] x = 8'hff;
  
    parameter STEP = 1;
  
    initial begin
            
      #STEP
      #STEP
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=ff

!2006-05-04 Thu

条件演算子

  module test_tb;
    reg  [7:0] a, b, c;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a == 0 ? b : c;
  
    initial begin
            a <= 8'h0; b <= 8'h00; c <= 8'hff;
      #STEP a <= 8'h1;
      #STEP a <= 8'h0;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h c=%h  x=%h", a, b, c, x);
  
  endmodule
で、
                     0 a=00 b=00 c=ff  x=00
                     1 a=01 b=00 c=ff  x=ff
                     2 a=00 b=00 c=ff  x=00

!2006-05-03 Wed

連接演算子

  module test_tb;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = {8{1'h1}};
  
    initial begin
      #STEP
      #STEP
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " x=%h", x);
  
  endmodule
で、
                     0 x=ff

!2006-05-02 Tue

連接演算子

  module test_tb;
    reg  [7:0]  a;
    wire [15:0] x;
  
    parameter STEP = 1;
  
    assign x = {a, 8'hff};
  
    initial begin
            a <= 8'h01;
      #STEP a <= 8'haa;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=01  x=01ff
                     1 a=aa  x=aaff
                     2 a=ff  x=ffff

!2006-05-01 Mon

連接演算子

  module test_tb;
    reg  [7:0]  a, b;
    wire [15:0] x;
  
    parameter STEP = 1;
  
    assign x = {a, b};
  
    initial begin
            a <= 8'h01; b <= 8'h11;
      #STEP a <= 8'haa; b <= 8'h33;
      #STEP a <= 8'hff; b <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=01 b=11  x=0111
                     1 a=aa b=33  x=aa33
                     2 a=ff b=ff  x=ffff

!2006-04-30 Sun

シフト

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a >> b;
  
    initial begin
            a <= 8'b01010101; b <= 8'h1;
      #STEP a <= 8'b01010101; b <= 8'h2;
      #STEP a <= 8'b01010101; b <= 8'h3;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%b b=%h  x=%b", a, b, x);
  
  endmodule
で、
                     0 a=01010101 b=01  x=00101010
                     1 a=01010101 b=02  x=00010101
                     2 a=01010101 b=03  x=00001010

!2006-04-29 Sat

シフト

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a << b;
  
    initial begin
            a <= 8'b01010101; b <= 8'h1;
      #STEP a <= 8'b01010101; b <= 8'h2;
      #STEP a <= 8'b01010101; b <= 8'h3;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%b b=%h  x=%b", a, b, x);
  
  endmodule
で、
                     0 a=01010101 b=01  x=10101010
                     1 a=01010101 b=02  x=01010100
                     2 a=01010101 b=03  x=10101000

!2006-04-28 Fri

リダクション EX-NOR

  module test_tb;
    reg  [7:0] a;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = ~^a;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h10;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=00  x=1
                     1 a=10  x=0
                     2 a=ff  x=1

!2006-04-27 Thu

リダクション EX-OR

  module test_tb;
    reg  [7:0] a;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = ^a;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h10;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=00  x=0
                     1 a=10  x=1
                     2 a=ff  x=0

!2006-04-26 Wed

リダクション NOR

  module test_tb;
    reg  [7:0] a;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = ~|a;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h10;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=00  x=1
                     1 a=10  x=0
                     2 a=ff  x=0

!2006-04-25 Tue

リダクション OR

  module test_tb;
    reg  [7:0] a;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = |a;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h10;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=00  x=0
                     1 a=10  x=1
                     2 a=ff  x=1

!2006-04-24 Mon

リダクション NAND

  module test_tb;
    reg  [7:0] a;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = ~&a;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h10;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=00  x=1
                     1 a=10  x=1
                     2 a=ff  x=0

!2006-04-23 Sun

リダクション AND
  module test_tb;
    reg  [7:0] a;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = &a;
  
    initial begin
            a <= 8'h00;
      #STEP a <= 8'h10;
      #STEP a <= 8'hff;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=00  x=0
                     1 a=10  x=0
                     2 a=ff  x=1

!2006-04-22 Sat

反転
  module test_tb;
    reg  [7:0] a;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = ~a;
  
    initial begin
            a <= 8'h55;
      #STEP a <= 8'h10;
      #STEP a <= 8'haa;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=55  x=aa
                     1 a=10  x=ef
                     2 a=aa  x=55

!2006-04-21 Fri

EX-NOR

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a ~^ b;
  
    initial begin
            a <= 8'h55; b <= 8'h33;
      #STEP a <= 8'h10; b <= 8'h01;
      #STEP a <= 8'haa; b <= 8'h55;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=55 b=33  x=99
                     1 a=10 b=01  x=ee
                     2 a=aa b=55  x=00

!2006-04-20 Thu

EX-OR

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a ^ b;
  
    initial begin
            a <= 8'h55; b <= 8'h33;
      #STEP a <= 8'h10; b <= 8'h01;
      #STEP a <= 8'haa; b <= 8'h55;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=55 b=33  x=66
                     1 a=10 b=01  x=11
                     2 a=aa b=55  x=ff

!2006-04-19 Wed

ビットAND

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a & b;
  
    initial begin
            a <= 8'h55; b <= 8'h33;
      #STEP a <= 8'h10; b <= 8'h01;
      #STEP a <= 8'haa; b <= 8'h55;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=55 b=33  x=11
                     1 a=10 b=01  x=00
                     2 a=aa b=55  x=00

!2006-04-18 Tue

ビットOR

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    assign x = a | b;
  
    initial begin
            a <= 8'h55; b <= 8'h33;
      #STEP a <= 8'h10; b <= 8'h01;
      #STEP a <= 8'haa; b <= 8'h55;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=55 b=33  x=77
                     1 a=10 b=01  x=11
                     2 a=aa b=55  x=ff

!2006-04-17 Mon

反転

  module test_tb;
    reg  a;
    wire x;
  
    parameter STEP = 1;
  
    assign x = !a;
  
    initial begin
            a <= 0;
      #STEP a <= 1;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h  x=%h", a, x);
  
  endmodule
で、
                     0 a=0  x=1
                     1 a=1  x=0

!2006-04-16 Sun

論理 AND
  module test_tb;
    reg  a, b;
    wire x;
  
    parameter STEP = 1;
  
    assign x = a && b;
  
    initial begin
            a <= 0; b <= 0;
      #STEP a <= 0; b <= 1;
      #STEP a <= 1; b <= 0;
      #STEP a <= 1; b <= 1;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=0 b=0  x=0
                     1 a=0 b=1  x=0
                     2 a=1 b=0  x=0
                     3 a=1 b=1  x=1

!2006-04-15 Sat

論理 OR
  module test_tb;
    reg  a, b;
    wire x;
  
    parameter STEP = 1;
  
    assign x = a || b;
  
    initial begin
            a <= 0; b <= 0;
      #STEP a <= 0; b <= 1;
      #STEP a <= 1; b <= 0;
      #STEP a <= 1; b <= 1;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=0 b=0  x=0
                     1 a=0 b=1  x=1
                     2 a=1 b=0  x=1
                     3 a=1 b=1  x=1

!2006-04-14 Fri

比較演算 ===

  module test_tb;
    reg  [7:0] a, b;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = a === b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h1x; b <= 8'h1x;
      #STEP a <= 8'h1z; b <= 8'h1z;
      #STEP a <= 8'h1x; b <= 8'hxx;
      #STEP a <= 8'h1z; b <= 8'hzz;
      #STEP a <= 8'h1x; b <= 8'h1z;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=00 b=00  x=1
                     1 a=01 b=05  x=0
                     2 a=1x b=1x  x=1
                     3 a=1z b=1z  x=1
                     4 a=1x b=xx  x=0
                     5 a=1z b=zz  x=0
                     6 a=1x b=1z  x=0

!2006-04-13 Thu

比較演算 ==

  module test_tb;
    reg  [7:0] a, b;
    wire       x;
  
    parameter STEP = 1;
  
    assign x = a == b;
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h1x; b <= 8'h1x;
      #STEP a <= 8'h1z; b <= 8'h1z;
      #STEP a <= 8'h1x; b <= 8'hxx;
      #STEP a <= 8'h1z; b <= 8'hzz;
      #STEP a <= 8'h1x; b <= 8'h1z;
      #STEP
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  x=%h", a, b, x);
  
  endmodule
で、
                     0 a=00 b=00  x=1
                     1 a=01 b=05  x=0
                     2 a=1x b=1x  x=x
                     3 a=1z b=1z  x=x
                     4 a=1x b=xx  x=x
                     5 a=1z b=zz  x=x
                     6 a=1x b=1z  x=x

!2006-04-12 Wed

parameter

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
    parameter [8*18:1] FMT = " a=%h b=%h  sum=%h";
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, FMT, a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule

!2006-04-11 Tue

ベクタ幅指定に式

  module test_tb;
    reg  [2*4-1:0] a, b;
    wire [7*1+0:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule

!2006-04-10 Mon

real

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    real r;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;     r = 0.0;
      #STEP a <= 1;     b <= 5;     r = 1.1;
      #STEP a <= 8'h80; b <= 1;     r = 2.2;
      #STEP a <= 8'hff; b <= 1;     r = 3.3;
      #STEP a <= 8'hff; b <= 8'hff; r = 4.4;
      $finish;
    end
  
    initial $monitor($stime, " %f  a=%h b=%h  sum=%h", r, a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 0.000000  a=00 b=00  sum=00
                     1 1.100000  a=01 b=05  sum=06
                     2 2.200000  a=80 b=01  sum=81
                     3 3.300000  a=ff b=01  sum=00

使ったことなかったなあ

!2006-04-09 Sun

integer

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    integer i;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;     i = 0;
      #STEP a <= 1;     b <= 5;     i = 1;
      #STEP a <= 8'h80; b <= 1;     i = 2;
      #STEP a <= 8'hff; b <= 1;     i = 3;
      #STEP a <= 8'hff; b <= 8'hff; i = 4;
      $finish;
    end
  
    initial $monitor($stime, " %d  a=%h b=%h  sum=%h", i, a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0           0  a=00 b=00  sum=00
                     1           1  a=01 b=05  sum=06
                     2           2  a=80 b=01  sum=81
                     3           3  a=ff b=01  sum=00

「=」でなくて、「<=」でも大丈夫みたい。
ふーむ、どういう意味を持つんだろう？
32 ビットの reg と同じ？？？

!2006-04-08 Sat

ベクタ範囲 実験

  module test_tb;
    reg  [7:0]  a, b;
    wire [15:8] x; // <- !!
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

!2006-04-07 Fri

マクロ 文字列

  `define FMT " a=%h b=%h  sum=%h"
  
  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, `FMT, a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

!2006-04-06 Thu

マクロ

  `define WIDTH 7
  
  module test_tb;
    reg  [`WIDTH:0] a, b;
    wire [`WIDTH:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [`WIDTH:0] a;
    input  [`WIDTH:0] b;
    output [`WIDTH:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

!2006-04-05 Wed

変数

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] \(^-^)/ ;
  
    parameter STEP = 1;
  
    top itop(a, b, \(^-^)/ );
  
    initial begin
            a <= 0;     b <= 0;
      #STEP a <= 1;     b <= 5;
      #STEP a <= 8'h80; b <= 1;
      #STEP a <= 8'hff; b <= 1;
      #STEP a <= 8'hff; b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, \(^-^)/ );
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

極悪だ…

!2006-04-04 Tue

値の表現

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a <= 0;           b <= 0;
      #STEP a <= 8'b00000001; b <= 8'b0000_0101;
      #STEP a <= 8'b00000001; b <= 8'o1;
      #STEP a <= 8'b00000001; b <= 8'o11;
      #STEP a <= 8'b00000001; b <= 8'b0000_010x;
      #STEP a <= 8'b00000001; b <= 8'b0000_010z;
      #STEP a <= 8'h80;       b <= 1;
      #STEP a <= 8'hff;       b <= 1;
      #STEP a <= 8'hff;       b <= 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=01 b=01  sum=02
                     3 a=01 b=09  sum=0a
                     4 a=01 b=0X  sum=xx
                     5 a=01 b=0Z  sum=xx
                     6 a=80 b=01  sum=81
                     7 a=ff b=01  sum=00

!2006-04-03 Mon

ファイルから読む

  `define N 4
  
  module test_tb;
    reg  [7:0]  a, b;
    wire [7:0]  x;
    reg  CLK, RESET;
    reg  [15:0] data[0:256];
    integer cnt;
  
    parameter STEP = 10;
  
    top itop(a, b, x);
  
    initial begin
      $readmemh("2006040300.txt", data);
      CLK <= 0; RESET <= 1;
    end
  
    always @(posedge CLK) begin
      if (RESET) begin
        cnt <= 0; RESET <= 0;
      end else if (cnt < `N) begin
        {a, b} <= data[cnt];
        cnt    <= cnt + 1;
      end else
        $finish;
    end
  
    always #(STEP/2) CLK = ~CLK;
  
    initial $monitor($stime, " cnt=%d  a=%h b=%h  sum=%h", cnt, a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
2006040300.txt
  00_00
  01_05
  80_01
  ff_01
で、
                     0 cnt=          x  a=xx b=xx  sum=xx
                     5 cnt=          0  a=xx b=xx  sum=xx
                    15 cnt=          1  a=00 b=00  sum=00
                    25 cnt=          2  a=01 b=05  sum=06
                    35 cnt=          3  a=80 b=01  sum=81
                    45 cnt=          4  a=ff b=01  sum=00

!2006-04-02 Sun

  module test_tb;
    reg  [7:0] A, B;
    wire [7:0] X;
  
    parameter STEP = 1;
  
    top itop(.a(A), .b(B), .x(X));
  
    initial begin
            A = 0;     B = 0;
      #STEP A = 1;     B = 5;
      #STEP A = 8'h80; B = 1;
      #STEP A = 8'hff; B = 1;
      #STEP A = 8'hff; B = 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", A, B, X);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00

!2006-04-01 Sat

  module test_tb;
    reg  [7:0] a, b;
    wire [7:0] x;
  
    parameter STEP = 1;
  
    top itop(a, b, x);
  
    initial begin
            a = 0;     b = 0;
      #STEP a = 1;     b = 5;
      #STEP a = 8'h80; b = 1;
      #STEP a = 8'hff; b = 1;
      #STEP a = 8'hff; b = 8'hff;
      $finish;
    end
  
    initial $monitor($stime, " a=%h b=%h  sum=%h", a, b, x);
  
  endmodule
  
  module top(a, b, x);
    input  [7:0] a;
    input  [7:0] b;
    output [7:0] x;
  
    assign x = a + b;
  
  endmodule
で、
                     0 a=00 b=00  sum=00
                     1 a=01 b=05  sum=06
                     2 a=80 b=01  sum=81
                     3 a=ff b=01  sum=00